Design and development of FPGA based low power pipelined 64-Bit RISC processor with double precision floating point unit

Kumar, J. Vijay; Nagaraju, Boya; Swapna, Chinthakunta; Thogata, Ramanjappa

doi:10.1109/iccsp.2014.6950008

Cited by 8 publications

(2 citation statements)

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“…Arithmetic Logic Unit The ALU is also called an execution unit [ 5 ], this unit comprises of arithmetic operations, relative operations, shifting operations and logic operations. The arithmetic operations comprise of addition, subtraction, multiplication, and division.…”

Section: B)mentioning

confidence: 99%

Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor

Divya¹,

Balasaraswathi²,

R³

et al. 2020

IJEAT

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The development of processors with sundry suggestions have been made regarding a exactitude definition of RISC, but the prosaic concept is that such a computer has a small set of simple and prosaic instructions, instead of an outsized set of intricate and specialized instructions. This project proposes the planning of a high speed 64 bit RISC processor. The miens of this processor consume less power and it contrives on high speed. The processor comprises of sections namely Instruction Fetch section, Instruction Decode section, and Execution section. The ALU within the execution section comprises a double-precision floating-point multiplier designed during a corollary architecture thus improving the speed and veracity of the execution. All the sections are designed using Verilog coding. Monotonous instruction format, cognate prosaic-purpose registers, and pellucid addressing modes were the other miens. RISC exemplified as Reduced Instruction Set Computer. For designing high-performance processors, RISC is considered to be the footing. The RISC processor has a diminished number of Instructions, fixed instruction length, more prosaic-purpose register which are catalogued into the register file, load-store architecture and facilitate addressing modes which make diacritic instruction execute faster and achieve a net gain in performance. Thus the cardinal intent of this paper is to consummate the veridicality by devouring less power, area and with merest delay and it would be done by reinstating the floating-point ALU with single precision section by floating- point double precision section. Video processing, telecommunications and image processing were the high end applications used by architecture

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Section: B)mentioning

confidence: 99%

Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor

Divya¹,

Balasaraswathi²,

R³

et al. 2020

IJEAT

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“…This section provides an idea about various developments in the past on branch predictors. J. V. Kumar et al in 2014 presented a low power pipelined 64-bit RISC processor containing a Floating Point Unit based on FPGA [7]. The development of this processor was carried out especially for carrying arithmetic operations on both fixed and floating point numbers, for branch and logical functions.…”

Section: Literature Surveymentioning

confidence: 99%

Performance Analysis of Branch Prediction Unit for Pipelined Processors

Panwar¹,

Kaur²,

Singh³

2015

IJCA

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The branch predictor plays a crucial role in the achievement of effective performance in microprocessors with pipelined architectures. This paper analyzes performance of branch prediction unit for pipelined processors. A memory of 512 bytes is designed for storing instructions. A 32 byte memory is designed for branch target buffer (BTB). This memory is utilized for storing history of the branch instructions. A Finite State Machine (FSM) is designed for branch predictor unit. It consists of four states: strongly taken, weakly taken, weakly not taken and strongly not taken. Prediction is done based on the status of FSM. If the state of FSM is weakly taken or strongly taken, then predictor guesses it as a taken condition else it is assumed to be not taken condition. When the execution of branch instruction is done for the first time the BTB stores the address of current instruction and also the address where it jumps. After this the current status of the FSM is updated accordingly. The program is executed using a branch predictor unit and also without a branch predictor unit. The latency of both the processors with a branch prediction unit and without is branch prediction unit is computed and compared. The simulation results validates that with branch prediction unit latency is decreased.

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