Design and development of memristor‐based RRAM

Abstract

A power-and variability-aware non-volatile resistive random access memory (RRAM) cell is presented. Non-volatility is achieved due to the use of a memristor as a memory element, which when integrated with a carbon nanotube field-effect transistor (CNFET) helps achieve tremendous robustness against process variation. The half-select issue, inherent in the 2T2M RRAM cell (state-of-the-art design based on the memristor) have been resolved and its circuit parameters have been compared with those of the proposed cell. Also, the proposed cell has been compared with the standard 6T SRAM (S6T) cell. The proposed cell shows 1.6×/4.08× narrower read delay/write delay variability compared with 2T2M. 5CNFET2M also shows 1.8× narrower read delay variability than that of S6T. Furthermore, the proposed cell shows 6.9× shorter write delay in comparison with the 2T2M RRAM cell. 5CNFET2M consumes 10 6 ×/1.34× lower power during hold mode compared with the conventional 6T static random access memory/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared with both the cells. All the simulated data, presented here are at the nominal supply voltage of 1 V. These improvements are gained at the expense of slightly longer read time compared with 2T2M/S6T and 31.3× longer write delay compared with S6T.

Reliable write assist low power SRAM cell for wireless sensor network applications

“…The read delay or read access time () for differential reading cells isestimated as mentioned in [10, 28–30]. On the other hand, for single‐ended reading cells like SEDF9T,read delay is estimated according to [12].…”

Nanoscale memristor devices: materials, fabrication, and artificial intelligence

“…This two-state behavior makes non-volatile memristors ideal for rewritable memory components, especially in a resistive random-access memory (RRAM) system. [41][42][43] For a volatile memristor, the resistance state can also be adjusted from one stage to another stage by applying an external voltage. However, unlike the non-volatile memristor, the resistance state cannot remain after the external voltage is removed.…”

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

“…T RA (read access time or read delay) is estimated from the time the wordline crosses 50% of its full swing to the time that one of the bitlines (BL/BLB) is discharged by 50 mV from its initial high level. 3,6,21,22 The value of the bitline capacitance and the amount of read current through the access transistor are the major factors which impact the T RA . All the 10T comparison cells and RHD12T have only one identically sized NMOS access transistor connected to each bitline.…”