Design and Emulation of All-Digital Phase-Locked Loop on FPGA

Radhapuram, Saichandrateja; Yoshihara, Takuya; Matsuoka, Toshimasa

doi:10.3390/electronics8111307

Cited by 9 publications

(3 citation statements)

References 23 publications

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“…TRNG designs based on an FIR-based ADPLL are created using VHDL. Considering all significant sources of entropy, including jitter form ADPLLs [16] and with ring oscillators, in addition to the flip-flop metastability state. The ring oscillator's jitter is in phase with the jitter created by the ADPLL used as an entropy source.…”

Section: Fpga Realization Of the Proposed Wireless Communication Netw...mentioning

confidence: 99%

Implementation of a secure wireless communication system using true random number generator for internet of things

Meitei

Kumar

2023

IJEECS

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This paper describes the design and implementation of an internet of thing (IoT)-based application that uses a true random number generator (TRNG) with an all digital phase locked loop (ADPLL) for secure wireless communication. Field programmable gate array (FPGA) boards were used on the transmitter and receiver sides and were interfaced with Esp8266 chips to wirelessly send and receive encrypted sensor data. The MQ-2 gas sensor and tracking sensor were connected to the FPGA board on the transmitter side, where data from the sensors was encrypted using the exclusive-OR (XOR) function and the TRNG architecture. The system can be controlled by users through a web browser served by the ThingSpeak cloud. The Artix-7 FPGA device is used to implement the proposed wireless communication system, for which design and synthesis were done using the Xilinx Vivado 2015.2 tool. The proposed system uses a low amount of power and is suitable for a standalone, highly secure TRNG-based IoT application. The National Institute of Standard and Testing (NIST SP 800-22) test showed that ADPLL with finite impulse response (FIR) filter-based TRNGs are better for encrypting IoT devices for secure wireless communication.

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Section: Fpga Realization Of the Proposed Wireless Communication Netw...mentioning

confidence: 99%

Implementation of a secure wireless communication system using true random number generator for internet of things

Meitei

Kumar

2023

IJEECS

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“…In [26] introduced quadrature oscillator model which comprises of four low-Q series LC tanks in a ring structure. It reduces distortion levels of delta-sigma architecture and performance rate significantly increased.…”

Section: Related Workmentioning

confidence: 99%

Design of Digital Frequency Synthesizer for 5G SDR Systems

C¹,

Munaswamy²

2022

IJRITCC

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The previous frequency synthesizer techniques for scalable SDR are not compatible with high end applications due to its complex computations and the intolerance over increased path interference rate which leads to an unsatisfied performance with improved user rate in real time environment. Designing an efficient frequency synthesizer framework in the SDR system is essential for 5G wireless communication systems with improved Quality of service (QoS). Consequently, this research has been performed based on the merits of fully digitalized frequency synthesizer and its explosion in wide range of frequency band generations. In this paper hardware optimized reconfigurable digital base band processing and frequency synthesizer model is proposed without making any design complexity trade-off to deal with the multiple standards. Here fully digitalized frequency synthesizer is introduced using simplified delay units to reduce the design complexity. Experimental results and comparative analyzes are carried out to validate the performance metrics and exhaustive test bench simulation is also carried out to verify the functionality.

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“…Furthermore, the author claims that a digital TRNG based on Meta-RO has a higher value of entropy, resulting in a nominal throughput of 140 Mbps being substantially increased. To demonstrate the efficacy and feasibility of ADPLL architecture, [14] uses an emulation technique. The proposed ADPLL emulation covers a broad frequency spectrum from 120 to 300 MHz, minimizing design time and complexity.…”

Section: Introductionmentioning

confidence: 99%

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

Meitei

Kumar

2022

SN Appl. Sci.

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This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented on the Artix 7(XC7A35T-CPG236-1) field programmable gate array (FPGA) board using the Xilinx Vivado v.2015.2 design suite. The coefficients of a 3rd-order broadcast low-pass digital FIR filter are computed using the Keiser window method. The MATLAB-FDA tool is used to calculate the filter coefficient. After reducing the bias in the sequence using the XOR-corrector post-processing approach, the suggested ADPLL-based TRNG designs created an unbiased stochastic random number with an overall throughput of 200 Mbps for both designs. The first proposed FIR-ADPLL-based TRNG design (FAT-1) consumes 0.072 W of power, whereas the second proposed FIR-ADPLL-based TRNG design (FAT-2) consumes 0.074 W. The resulting bitstream is verified for randomness using national institute of standards and technology (NIST) test following post-processing. Digital storage oscilloscope (DSO) is interfaced to the Artrix-7 FPGA board in order to capture the TRNG output waveforms. Both the proposed FIR-based ADPLL-TRNG designs passed the NIST SP 800-22 test, indicating that they are well-suited for a variety of industrial applications, including network security, cybersecurity, banking security, smart cards, radio-frequency identification tags, Internet of Things, and Industrial Internet of Things.

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Design and Emulation of All-Digital Phase-Locked Loop on FPGA

Cited by 9 publications

References 23 publications

Implementation of a secure wireless communication system using true random number generator for internet of things

Implementation of a secure wireless communication system using true random number generator for internet of things

Design of Digital Frequency Synthesizer for 5G SDR Systems

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

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