Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF

Thirumoorthi, Madhan; Jovanović, Marko; Mirhassani, Mitra; Khalid, Mohammed

doi:10.1109/tvlsi.2021.3111588

Cited by 12 publications

(4 citation statements)

References 33 publications

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“…Hence, the RO of odd-n delay units generates n 1 + n 3 + n 5 + ... + n n oscillating frequencies. The architectural variances in CROPUF primarily revolve around two key design elements: the nature of the delay unit and the inclusion of supplementary circuitry, which enhances entropy [18], reliability [17], and resistance to attacks [19]. Consequently, the lightweight designs of CROPUF are focused on these aspects to reduce resource consumption.…”

Section: Related Workmentioning

confidence: 99%

“…Nevertheless, the complex hardware nature of XOR constrains its application as a delay unit in systems with limited resources. Chaotic-BR-PUF [19] is an iterative-based PUF featuring a delay unit composed of two NOR gates, Mux, and DeMux. Chaotic-BR-PUF employs a chaotic function to obfuscate valid CRPs and eliminate modeling attacks, but this adds more complexity to the design.…”

Section: Related Workmentioning

confidence: 99%

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Boosted PUF: Boosting Efficiency and Resilience in Configurable RO PUF for IoT Devices

Abulibdeh,

Saleh,

Mohammad

et al. 2024

Preprint

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In the realm of Internet of Things (IoT) security, the Physical Unclonable Function (PUF) emerges as a viable solution for generating individualized secure keys. These keys play a vital role in authentication, chip protection, and supply chain security, serving as crucial safeguards for resource-constrained IoT devices. This work introduces Boosted Configurable Ring Oscillator PUF (BC-PUF), an area-efficient variant of CROPUF that suits resource-constrained IoT devices. Additionally, BC-PUF employs an absorbent approach for the intermediate responses to optimize the utilization of CMOS delay configurations. Moreover, BC-PUF mitigates the risk of Machine Learning (ML)-based modeling attacks. BC-PUF is a multi-bit response architecture that has been developed, analyzed, and evaluated across 50 FPGAs, from each dataset of 10K Challenge-Response Pairs (CRPs) is extracted. Experimental results report average values of 50.2%, 40.4%, 42%, 3.925%, and 83% for uniformity, diffuseness, uniqueness, reliability, and Shannon entropy, respectively. In comparison to state-of-the-art designs, the BC-PUF design achieves area reductions ranging from 15% to 96.7% across various architectures and implementations, along with a power reduction of 9.7%. Moreover, BC-PUF demonstrates resilience against ML-based attacks, achieving a prediction accuracy of 51%.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Boosted PUF: Boosting Efficiency and Resilience in Configurable RO PUF for IoT Devices

Abulibdeh,

Saleh,

Mohammad

et al. 2024

Preprint

View full text Add to dashboard Cite

show abstract

“…A bistable PUF [22] is a type of PUF with a crosscoupled circuit structure as its core. The bistable PUF circuit is always in a stable state when not triggered by an external excitation signal and jumps from the current stable state to another stable state when triggered by the challenge signal.…”

Section: Bistable Puf Circuit Structurementioning

confidence: 99%

A compact weak PUF circuit based on MOSFET subthreshold leakage current

Xie

Wang

et al. 2022

IEICE Electron. Express

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Owing to the large area and power consumption of traditional physically unclonable function (PUF)circuits, they are susceptible to interference from environmental factors. A compact PUF circuit design scheme is proposed by analyzing the circuit structure and sub-threshold leakage current deviation characteristics of a bistable PUF. First, the current-voltage sensitive characteristics of a transistor in the subthreshold operating region are utilized. Next, to improve the output response speed and the uniqueness of the characteristic information of the PUF circuit, the proposed PUF circuit is designed which combines with the positive feedback and RS latch characteristics. Finally, simulation results based on the TSMC 65 nm CMOS process show that the PUF has good uniqueness, randomness, and reliability. The cell layout area, the bit error rate (BER) in the worst case, and the energy consumption are 0.177 μm 2 , 2.8%, and 8.976 fJ/bit respectively.

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“…There are many ways to classify PUFs, which are usually classified as weak or strong based on their ability to generate CRPs [5]. The CRPs generated by weak PUF are difficult to be obtained by the outside world and have a limited number, mainly including SRAM PUF [6], BR PUF [7], Glitch PUF [8], etc. ; strong PUF can generate exponential number of CRPs, mainly including Arbiter PUF (APUF), MPUF [9] and IPUF [10].…”

Section: Introductionmentioning

confidence: 99%

A highly stable XOR APUF based on deviation signal screening mechanism

Zhai,

Wang,

et al. 2023

IEICE Electron. Express

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By using the XOR method to obfuscate response of Arbiter PUFs (APUFs), the ability to resist machine learning (ML) modeling attacks can be improved, but this method will reduce the stable of PUF to a certain extent, making PUF lose usability. In view of this, a highly stable XOR APUF (HS-XOR APUF) circuit is proposed by studying the generation mechanism of unstable response bits and the screening characteristics of the logic gates delay signals. First, the maximum and minimum delay signals are screened with AND/OR gate to generate highly stable response bits; Then, by inserting a inverter in the APUF switch unit, the delay time of the signal is increased, and the influence of environmental factors on the comparison signal with small delay deviation is weakened; Finally, the FPGA experimental results show that the response stability of HS-XOR APUF is rarely affected by the count of XOR units, and the AND/OR gate delay signal screening structure is simple and consumes a small amount of hardware resources, which can be widely used in the fields of information security.

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Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF

Cited by 12 publications

References 33 publications

Boosted PUF: Boosting Efficiency and Resilience in Configurable RO PUF for IoT Devices

Boosted PUF: Boosting Efficiency and Resilience in Configurable RO PUF for IoT Devices

A compact weak PUF circuit based on MOSFET subthreshold leakage current

A highly stable XOR APUF based on deviation signal screening mechanism

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