Design and Evaluation of an FPGA-ADC Prototype for the PET Detector Based on LYSO Crystals and SiPM Arrays

Ma, Cong; Dong, Xue; Yu, Li; Wubin, Wang,; Zhao, Xiaokun; Li, Xing; Huang, Zhenqing; Wu, Guocheng; Lu, Lei; Chen, Hansheng

doi:10.1109/trpms.2021.3062362

Cited by 13 publications

(6 citation statements)

References 44 publications

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“…The work of [ 2 ] achieved an 800 MS/s sample rate at only 3.9-bit ENOB for a 100 MHz analog signal input. The ADC presented in this work achieves the highest ENOB, while operating at a sampling rate higher than in [ 18 , 19 , 35 ]. Moreover, unlike the other FPGA ADCs in Table 1 , the proposed ADC does not need external components.…”

Section: Resultsmentioning

confidence: 99%

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Zhang

Zhao

Chen

et al. 2022

Sensors

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A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

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Section: Resultsmentioning

confidence: 99%

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Zhang

Zhao

Chen

et al. 2022

Sensors

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“…FPGA ADC implementations are usually based on tapped-delay line (TDL) TDCs to achieve high resolution, but the encoding of detected edges consumes a lot of FPGA resources [23,24]. Meanwhile, due to the nonlinearity and channel inconsistency of the TDL TDC itself and the phase deviation of the TDC's clock and ramp waves, several manual calibrations using external calibration signals need to be performed before an FPGA ADC works properly [22,23].…”

Section: Multicycle-encoding Fpga Adc With Automated Calibrationmentioning

confidence: 99%

“…There are two commonly used charge measurement methods in PET electronics, namely direct digitization through an ADC chip [15] with digital peak detection or integration, and time-overthreshold (TOT) with TDC digitization [16]. Several FPGA-based measurement methods have also been proposed on the basis of these two methods [24,28,29]. Although TOT circuits are generally simpler than ADC circuits, TOT-based digitization has the disadvantages of poor nonlinearity and resolution.…”

Section: Introductionmentioning

confidence: 99%

“…The application of FPGA ADCs in PET energy measurement was proposed in [24], and a 3-channel digital signal processor prototype based on a 25 Msps FPGA ADC was reported, which had a charge resolution better than 6.0% in the input range from 400 mV to 4 V when combined with a CR-RC3 shaping circuit. In small animal PET electronics, there is a need for higher channel integration and measurement resolution, so further research and optimization of FPGA ADCs is necessary to reduce the requirements on the FPGA's logic resources and improve reusability.…”

Section: Introductionmentioning

confidence: 99%

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Prototype of a digitizer module based on multicycle-encoding FPGA ADC for a small animal PET

et al. 2023

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Current research in small animal positron emission tomography (PET) scanners focus on obtaining better spatial resolution and higher sensitivity. These enhancements of scanner performance result in a corresponding increase in the complexity of the electronics, which usually manifests through an increase in the number of electronics channels. Analog-to-digital converters (ADCs) implemented in field programmable gate arrays (FPGAs) are an effective way to simplify electronics complexity. In this paper, a resource-saving multicycle-encoding structure of an FPGA-based ADC with automated calibration is proposed, which achieves a sampling rate of 250 Msps. A digitizer module prototype containing 64 charge measurement channels based on the FPGA ADC is designed using a Kintex-7 FPGA. The effective number of bits (ENOB) achieved using the FPGA ADC is 4.26 bits under a 10.0555 MHz sine wave input. The charge measurement resolution of each channel is better than 5‰ full width half maximum under a 0.8 V signal input and 3% under inputs in the range 0.1 V to 1.2 V. The integral nonlinearity of each channel is within ± 1%.

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“…Researches has proved that the non-linearity of the SiPM outputs can be corrected according to the below saturation models [18,19].…”

Section: Energy Correction Algorithmmentioning

confidence: 99%

An FPGA Based energy correction method for one-to-one coupled PET detector: model and evaluation

Zhao

Gao³

et al. 2022

J. Inst.

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A PET scanner based on silicon photomultipliers (SiPMs) has been widely used as an advanced nuclear medicine imaging technique that yields quantitative images of regional in vivo biology and biochemistry. The compact size of the SiPM allows direct one-to-one coupling between the scintillation crystal and the photosensor, yielding better timing and energy resolutions than the light sharing methods that have to be used in photomultiplier tube (PMT) PET systems. To decrease the volume of readout electronics, a front-end multiplexer with position decoder is a common choice for the one-to-one system without a highly integrated application specific integrated circuit (ASIC). However, in this case we cannot measure each crystal's deposited energy inspired by an annihilation photon, so the inter-crystal scatter (ICS) events will lead to the crystal mispositioning and then deteriorate the detector intrinsic resolution. Besides, considering the events rejection within the energy window resulting from the gain dispersion and non-linear outputs of the SiPMs, an energy correction mechanism is needed. Yet, lack of the information of each crystal's energy will introduce large energy correction error for the ICS events. For this issue, an online energy correction mechanism implemented on a Kintext-7 Field Programmable Gate Array (FPGA) device is presented in this paper. Experiments in the laboratory were performed using an 8 × 8 segmented LYSO crystals coupled with an 8 × 8 SiPM (J-series, from ON Semiconductor) array which is under 22Na point source excitation. Test results indicate that both the energy of the non-ICS and ICS events can be precisely corrected and the energy resolution is better than 12 %. We also applied this method to an actual clinical PET scanner under a 68Ge line source to verify its multi-channel reliability.

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Design and Evaluation of an FPGA-ADC Prototype for the PET Detector Based on LYSO Crystals and SiPM Arrays

Cited by 13 publications

References 44 publications

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Prototype of a digitizer module based on multicycle-encoding FPGA ADC for a small animal PET

An FPGA Based energy correction method for one-to-one coupled PET detector: model and evaluation

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