Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates

Channi, Manjot Kaur; Kumar, Manoj

doi:10.1109/icic3s61846.2024.10602861

2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S) 2024

DOI: 10.1109/icic3s61846.2024.10602861

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Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates

Manjot Kaur Channi,

Manoj Kumar

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Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates

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