Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications

Naveenkumar, R; Sivamangai, N. M.; Napolean, A.; Priya, S. Sridevi Sathya

doi:10.1007/s10836-022-06034-7

Cited by 14 publications

(5 citation statements)

References 28 publications

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“…In terms of uniqueness and uniformity [81,90,91], it is evident that the delay-based arbiter PUF technique beats the others [92][93][94], but when compared to other arbiter PUF designs, the dependability of delay-based arbiter PUF [91] exceeds them.…”

Section: Performance Evaluation and Comparative Analysismentioning

confidence: 97%

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Lata,

Cenkeramaddi

2023

Cryptography

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Field-programmable gate arrays (FPGAs) have firmly established themselves as dynamic platforms for the implementation of physical unclonable functions (PUFs). Their intrinsic reconfigurability and profound implications for enhancing hardware security make them an invaluable asset in this realm. This groundbreaking study not only dives deep into the universe of FPGA-based PUF designs but also offers a comprehensive overview coupled with a discerning comparative analysis. PUFs are the bedrock of device authentication and key generation and the fortification of secure cryptographic protocols. Unleashing the potential of FPGA technology expands the horizons of PUF integration across diverse hardware systems. We set out to understand the fundamental ideas behind PUF and how crucially important it is to current security paradigms. Different FPGA-based PUF solutions, including static, dynamic, and hybrid systems, are closely examined. Each design paradigm is painstakingly examined to reveal its special qualities, functional nuances, and weaknesses. We closely assess a variety of performance metrics, including those related to distinctiveness, reliability, and resilience against hostile threats. We compare various FPGA-based PUF systems against one another to expose their unique advantages and disadvantages. This study provides system designers and security professionals with the crucial information they need to choose the best PUF design for their particular applications. Our paper provides a comprehensive view of the functionality, security capabilities, and prospective applications of FPGA-based PUF systems. The depth of knowledge gained from this research advances the field of hardware security, enabling security practitioners, researchers, and designers to make wise decisions when deciding on and implementing FPGA-based PUF solutions.

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Section: Performance Evaluation and Comparative Analysismentioning

confidence: 97%

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Lata,

Cenkeramaddi

2023

Cryptography

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“…A-PUF faces challenges in uniqueness and dependability due to physical layout constraints, particularly on FPGAs. To address these issues and other limitations described in [180], FFAPUF is introduced with a compact design, high uniqueness, and reliability, suitable for FPGA implementation. A-PUF on FPGAs faces issues with vulnerability to machine learning (ML) attacks and diminished uniqueness.…”

Section: B Physical Unclonable Functions(pufs)mentioning

confidence: 99%

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Srinivas,

Elango

2024

IEEE Access

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To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this convergence poses a significant security challenge, as adversaries can exploit it to extract unauthorized information, compromise system performance, and obtain secret keys. Meanwhile, traditional CMOS features have limitations in addressing hardware vulnerabilities and security threats, so promising post-silicon technologies offer potential solutions. Beyond-CMOS technologies offer avenues to fortify hardware security through distinct physical properties and nontraditional computing paradigms. These advancements bolster authentication processes, enhance key generation mechanisms, ensure hardware integrity and fortify resilience against side-channel attacks, hardware Trojans and quantum-resistant cryptography in securing hardware systems. This article provides a detailed review of hardware security, encompassing the identification and mitigation of threats, the implementation of robust countermeasures, the utilization of innovative primitives, countermeasures, various methodologies and distinct features offered by emerging technologies to resist hardware threats.Moreover, strategies to address challenges, explore future directions, and outline plans for achieving further research outcomes have been put forth in this field.

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“…Additionally, combining multiple PUF instances is an important way to enhance the resistence of machine learning attack, such as XOR-PUF proposed in [5] combines the output responses of multiple APUF instances through XOR operations, which significantly improves the resistence of machine learning attack, but overly high XOR combinations leads to negative impact on the reliability of PUFs [21]; IPUF [22] introduces the outputs of XOR-PUFs into another set of XOR-PUFs as input challenges, which not only improves machine learning resistence, but also avoids the reliability degradation problem brought by overly high XOR combinations, however, IPUF is cracked by machine learning algorithms adopting the divide-and-conquer approach in [23]; OAX-PUF [24] replaces part of XOR logic gate in XOR-PUF with a combination of AND gates and OR gates, making some machine learning algorithms against XOR-PUF less effective, such as logistic regression, but it still vulnerable to the latest deep learning attacks.…”

Section: Introductionmentioning

confidence: 99%

A machine learning resistant PUF circuit adjustment method based on strict avalanche criterion

Xie,

Liang,

Cao

et al. 2024

IEICE Electron. Express

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Physical Unclonable Functions(PUF) is a kind of hardware security primitive which is vulnerable to machine learning attacks. This work proposed a structural adjustment method based on Arbiter PUF(APUF), with the Strict Avalanche Criterion (SAC) as a guideline, improves the SAC property by leading multiple arbiters to obfuscation circuits at intermediate positions; quantitative analysis of SAC property by optimization method leads to the best placement of arbiters, which improves the utilization of resources. FPGA experiment results show that the proposed method significantly improves PUF's resistance to machine learning attack such as logistic regression, evolutionary strategies and deep neural networks, and requires lower hardware resources overhead compared to other similar APUF based schemes with the same attack resistance.

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Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications

Cited by 14 publications

References 28 publications

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

A machine learning resistant PUF circuit adjustment method based on strict avalanche criterion

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