Design and FPGA implementation of multiplierless comb filter

Abstract

Summary The main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements; therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first‐order and second‐order all‐pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round‐off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan‐6 and Virtex‐6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright © 2017 John Wiley & Sons, Ltd.

Reconfigurable Filter Bank Design Techniques for Hearing Aid Performance Improvement

“…Few suggestions for further performance improvement in terms of area and power includes replacing multipliers with adders or use of multiplier less filters like cascaded integrator comb (CIC), replacing adders with 4:2 compressors in FIR filter design for improved are and speed [19], reducing the effective word length of filter channels coefficients, adopting Multi-rate architecture and usage of approximate multipliers for filter. Variable Bandwidth Filters with farrow structure, FIR filter realized using transposed direct form, adopting Canonical signed digit space [4] and Distributed Arithmetic based FIR filter can be good techniques for complexity reduction and speed improvement.Further, applying signal processing algorithms like Multiband compression, Speech enhancement, Prescription-fitting for reduced inter-band interference [35] can surely result in improved speech intelligibility.Apart from above mentioned techniques forimprovement, it has been observed that existing devices for people with hearing misfortune mainly focusses on either of the three arenas of Hearing viz. Hearing Restoration, Enhancement or Assistance.…”

FPGA‐based system for effective IQ imbalance mitigation of RF power amplifiers

“…The last component to address is the multiplier that calculates the power exponents for each nonlinearity order considering that the input signal is normalized. The bit width remains the same throughout the exponent series calculation with multipliers computation …”

“…The bit width remains the same throughout the exponent series calculation with multipliers computation. 25,26…”

Optimal design of minimum multiplier lattice wave digital lowpass filter using metaheuristic techniques

“…The LWDF structures exhibit various attractive properties such as low coefficient sensitivity and consequently, the low accuracy requirements for the register word length, higher dynamic range, higher overflow level, lower round-off noise, assurance of stability, and good non-linear properties under finitearithmetic conditions where the effects of rounding, truncation, and overflow are present [7][8][9]. LWDF structures are preferent for realisation of notch-comb filter, LP-highpass filter, integrator, differentiator, and Hilbert transformers [10][11][12][13][14] as their ensuing structures are highly modular, have low sensitivity to coefficient variation, and minimal hardware utilisation.…”