Design and FPGA Implementation of Vedic Notch and Peak Filters

The demand for quick and effective real-time digital signal processing (DSP) applications has increased due to the rapidly advancing technology. Digital signal processors, or DSPs, are essential to several engi- neering specialties. In DSPs, quick multiplication is crucial for operations like Fourier transformations and convolution. One of the fundamental arithmetic processes required by all applications is multiplication. To increase their speed, numerous multiplier designs have been created. Vedic multipliers are among the quick- est and lowest power multipliers compared to array and booth multipliers which are the result of decades of intensive research. The Vedic Multiplier works with sixteen sutras, or algorithms, most of which are for logical processes. Since several of them have been proposed utilizing the Urdhava Tiryakbhyam sutra, they are the fastest and most efficient. This paper's goal is to summarise the many uses of Vedic Multiplier in the broad field of digital signal processing such as image processing, with a focus on the various ways that Vedic Multiplier designs that are now in use have been modified to improve speed and performance metrics.

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Performance Analysis of Vedic Multiplier in Hardware Implementation of Biomedical Applications

Agarwal

2024

International Journal of Innovative Science and Research Techno

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As technology advances at a rapid pace, there is an increasing need for real-time digital signal processing (DSP) applications that are efficient and swift. DSPs, or digital signal processors, are crucial components of several engineering disciplines. For processes like convolution and Fourier transforms in DSPs, rapid multiplication is essential. Multiplication is one of the basic mathematical operations used by all applications. Many different multiplier designs have been developed to boost their speed. When compared to array and booth multipliers—the products of decades of hard research—vedic multipliers are among the fastest and lowest power multipliers. The sixteen sutras, or algorithms, that the Vedic Multiplier uses are primarily logical procedures. They are the fastest and most effective because several of them have been proposed using the Urdhava Tiryakbhyam sutra. The purpose of this study is to provide an overview of the numerous biomedical applications of Vedic Multiplier in the wide field of digital signal processing, including denoising of Electrocardiogram (ECG) and Electroencephalogram ( EEG) signal. Particular attention is paid to how current Vedic Multiplier designs have been altered to increase speed and performance metrics.

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Design and FPGA Implementation of Vedic Notch and Peak Filters

Cited by 3 publications

References 17 publications

Filtering analysis of soil radon and thoron time series data

Filtering analysis of soil radon and thoron time series data

Performance Analysis of Vedic Multiplier in Signal Processing Applications

Performance Analysis of Vedic Multiplier in Hardware Implementation of Biomedical Applications

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