Design and hardware architectures for dynamic Huffman coding

Liu, L.-Y.; Wang, J.-F.; Wang, R.-J.; Lee, J.-Y.

doi:10.1049/ip-cdt:19952157

Cited by 13 publications

(5 citation statements)

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“…3 MHz. An adaptive Huffman code implementation in hardware is presented in [26]. This design is based on content addressable memory (CAM) modules to speed up the tree adaptation process and achieves a throughput of almost 1 bit/cycle.…”

Section: Introductionmentioning

confidence: 99%

Gbit/s lossless data compression hardware

Nunez

Jones

2003

IEEE Trans. VLSI Syst.

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This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.

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Section: Introductionmentioning

confidence: 99%

Gbit/s lossless data compression hardware

Nunez

Jones

2003

IEEE Trans. VLSI Syst.

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“…The data is stored securely, as all selected compression codecs are lossless. The gzip and deflate codecs use the deflate algorithm as a combination of lz77 and Huffman Coding [10]. The lz77 compression algorithm replaces duplicate bit positions regarding their previous positions.…”

Section: Background and Motivationmentioning

confidence: 99%

Performance Optimization System for Hadoop and Spark Frameworks

Astsatryan

Kocharyan²,

Hagimont³

et al. 2020

Cybernetics and Information Technologies

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The optimization of large-scale data sets depends on the technologies and methods used. The MapReduce model, implemented on Apache Hadoop or Spark, allows splitting large data sets into a set of blocks distributed on several machines. Data compression reduces data size and transfer time between disks and memory but requires additional processing. Therefore, finding an optimal tradeoff is a challenge, as a high compression factor may underload Input/Output but overload the processor. The paper aims to present a system enabling the selection of the compression tools and tuning the compression factor to reach the best performance in Apache Hadoop and Spark infrastructures based on simulation analyzes.

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“…In addition, each symbol at a leaf node is assigned a weight that depends on the relative frequency of the symbol within the source message, and each non-leaf node contains a weight value that is the sum of all the weights of the leaves lying below it. Current Huffman coding methods employ the symbol weights for constructing the Huffman tree, which requires considerable computation time for determining the relative position of each symbol on the tree [6,7]. Therefore, the present work employs the data structure elements proposed in the previous section to construct the Huffman tree, which simplifies the complexity of the construction process by synchronously construct- Fig.…”

Section: Encoding Algorithmmentioning

confidence: 99%

Efficient VLSI Huffman encoder implementation and its application in high rate serial data encoding

Wei

Zhang

2017

IEICE Electron. Express

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Abstract:In this paper, we present a new data structure element for constructing a Huffman tree, and a new algorithm is developed to improve the efficiency of Huffman coding by constructing the Huffman tree synchronously with the generation of codewords. The improved algorithm is adopted in a VLSI architecture for a Huffman encoder. The VLSI implementation is realized using the Verilog hardware description language and simulated by Modelsim. The proposed scheme achieves rapid coding speed with a gate count of 9.962 K using SMIC 0.18 micron standard library cells.

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Design and hardware architectures for dynamic Huffman coding

Cited by 13 publications

References 0 publications

Gbit/s lossless data compression hardware

Gbit/s lossless data compression hardware

Performance Optimization System for Hadoop and Spark Frameworks

Efficient VLSI Huffman encoder implementation and its application in high rate serial data encoding

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