Design and implementation of 16 tap FIR filter for DSP Applications

Sameeksha, N; S, Pannaga Shree B; Meghana, Y P; Chavan, Arunkumar P; Aradhya, H. V. Ravish

doi:10.1109/icaecc.2018.8479480

Cited by 17 publications

(13 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…33 Literature reports architectures optimizing the adder structure to enhance the overall performance. Techniques such as multiplexer-based carry increment adder (CIA) 34 and branched-tree algorithm 35 are reported, targeting the combinational path delay. However, it must be pointed out that there is no critical requirement for high speed in filtering biomedical signals such as ECG.…”

Section: Review Of Recent Literature On Hardware Implementation Of Fi...mentioning

confidence: 99%

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

The design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature.

show abstract

Section: Review Of Recent Literature On Hardware Implementation Of Fi...mentioning

confidence: 99%

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…It assists in reducing the circuit's clock period, power consumption, and logic synthesis. It is used to boost the circuit's clock rate [27]. Additionally, it is utilized to reduce switching, which may result in effective power dissipation in static CMOS circuits [28].…”

Section: The Proposed Pipelining and Retiming Topologiesmentioning

confidence: 99%

Distributed Arithmetic RNS-based FIR Filter Design using Pipelining and Retiming Methods for High-Speed DSP Systems

Balaji

N²

2022

Preprint

View full text Add to dashboard Cite

This work presents a way to increase the throughput and energy efficiency of finite impulse response (FIR) filters through the efficient application of retiming and two-level pipelining. It is a challenge to increase the filter's throughput and energy efficiency while reducing latency and hardware complexity. The operations of addition and multiplication are divided using two-level pipelining. The break addition procedure is retimed. The architecture of m-tap filter (4-tap, 8-tap, 16-tap, 32-tap, and 64-tap) with n-bit input word length (4-bit, 8-bit, 16-bit, and 32-bit) Pipelined Retiming delay generation Filters (PRF), were designed. The proposed distributed arithmetic-based FIR Filter with pipelining has produced the least delay of 2.564ns for 4-tap with 8-bit input, and the maximum delay of 56.040ns for 64-tap with 32-bit word length. The proposed distributed arithmetic-based FIR Filter with retiming method has produced the least delay of 0.687ns for 4-tap with 8-bit input, and the maximum delay of 4.535ns for 64-tap with 32-bit word length. When compared with the pipelining method, the delay has been decreased by 73.20% for 4-tap with 8-bit input and 91.90% for 64-tap with 32-bit word length.

show abstract

“…Adder 5 represents the square root CSLA in [20]. Adder 6 represents the CIA in [35]. Adder 7 represents the CSLA in [17].…”

Section: Performance Comparisonmentioning

confidence: 99%

“…Filter 7 represents the two‐level PFF (FIR‐PIP2) used for the adaptive filter design 3 in [37]. Filter 8 represents the FIR filter using incremental adders (FIR‐CIA) in [35]. Filter 9 represents the FIR filter using the Wallace tree multipliers (FIR‐WM) in [33].…”

Section: Performance Comparisonmentioning

confidence: 99%

“…Krishnamurthy , et al [34] have designed FIR filter using novel pipelined bypass multiplier and carry look‐ahead adders and achieved improvement in delay in comparison with conventional direct form FIR filter at the cost of increased hardware complexity. Rai , et al [35] have designed 16‐tap FIR filter using carry increment adders (CIAs) and Vedic multipliers. They achieved improvement in delay and energy efficiency in comparison with conventional direct form FIR filter at the cost of increased area.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High throughput FIR filter architectures using retiming and modified CSLA based adders

Patali

Kassim

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add-multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power-delay product and area-delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.

show abstract

Design and implementation of 16 tap FIR filter for DSP Applications

Cited by 17 publications

References 8 publications

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Distributed Arithmetic RNS-based FIR Filter Design using Pipelining and Retiming Methods for High-Speed DSP Systems

High throughput FIR filter architectures using retiming and modified CSLA based adders

Contact Info

Product

Resources

About