Design and Implementation of 256-Point Radix-4 100 Gbit/s FFT Algorithm into FPGA for High-Speed Applications

Polat, Gökhan; Öztürk, Sıtkı; Yakut, Mehmet

doi:10.4218/etrij.15.0114.0678

Cited by 20 publications

(6 citation statements)

References 5 publications

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“…After multiplexing operations, data at even-numbered branches are delayed one clock cycle to align the data. By applying (23) to (22), the data order at the input of part D becomes P 1 , according to (17), which is the expected order at the input of the PEs for the first FFT iteration.…”

Section: Proposed 64-parallel 4096-point Memory-based Fft Architecturementioning

confidence: 99%

“…Another approach to reduce the latency in both memory-based and pipelined FFTs is to increase the parallelization of the architecture. In fact, this approach has been widely used for pipelined FFTs, where highly parallel [15], [16], [17], [18], [19] and fully-parallel [20], [21], [22] FFT architectures have been presented. Nevertheless, the area of these architectures is extremely large.…”

Section: Introductionmentioning

confidence: 99%

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Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G

Kaya,

Garrido

2023

IEEE Trans. Circuits Syst. I

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This paper presents a novel 64-parallel 4096-point radix-2 memory-based fast Fourier transform (FFT) architecture for 6G. This approach is the first one to use 64 parallel branches in memory-based architectures. The challenge of designing a memory-based FFT with such a high parallelization has been accomplished by paying special attention to the large number of memories in parallel. Their control has been simplified by using the same read and write address for all of them thanks to the perfect shuffle permutation, and they are organized in groups to eliminate unnecessary registers. Likewise, a novel design for the rotation memories allows for reusing rotation coefficients among parallel rotators, and a new design for the circular counter that controls the architecture is presented. The proposed FFT architecture has been implemented on a Virtex 7 field-programmable gate array (FPGA). Experimental results reveal that the proposed architecture achieves the lowest latency in clock cycles and the highest throughput in samples per clock cycle among memory-based FFT architectures so far.

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Section: Proposed 64-parallel 4096-point Memory-based Fft Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G

Kaya,

Garrido

2023

IEEE Trans. Circuits Syst. I

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“…FPGA, on the other hand, has a much higher degree of parallelism than DSP and can use rich logic resources through a parallel flow design approach to obtain a great increase in processing speed with less power consumption, which is more suitable for real-time processing of high-volume streaming data in embedded application scenarios. FPGA also has a configurable hardware structure, which makes them more flexible in pre-design and verification [ 5 ]. Therefore, the implementation of large point FFT using FPGA is a more enthusiastic way for researchers in the field of high-performance signal processing or high-speed computing.…”

Section: Introductionmentioning

confidence: 99%

Design of Spectrum Processing Chiplet Based on FFT Algorithm

2023

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With the rapid development of electronic information and computer science, the fast Fourier transform (FFT) has played an increasingly important role in digital signal processing (DSP). This paper presented a spectrum processing chiplet design method to solve slow speed, low precision, and low resource utilization in spectrum processing of general-purpose spectrum chips and field programmable gate array (FPGA). To realize signal processing, the Radix-2 4096-point FFT algorithm with pipeline structure is used to process spectral signals extracted from the time domain. To reduce the harm caused by spectrum leakage, a windowing module is added to optimize the input data, and the clock gating unit (CGU) is used to perform low-power management on the entire clock reset. The result shows the chiplet takes 0.368 ms to complete a 4096-point frequency sweep under a clock frequency of 61.44 MHz. The chiplet significantly improves speed and accuracy in spectrum processing, which has great application potential in wireless communication.

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“…In the past, fully parallel FFTs have been employed in applications such as high definition (HD) streaming, chromatic dispersion filtering, beamspace processing and radar [4][5][6][7]. So far, only a few fully parallel architectures, viz., radix-2 k , radix-4 and split-radix (SR) have been reported in the literature either to realise high-throughput or low-energy [4][5][6][7]. The SRFFT has the least computational complexity among its peers, especially in number of non-trivial multiplications [5].…”

mentioning

confidence: 99%

“…This prevents the SRFFT from taking advantage of its inherent low computational complexity. The designs [4,5] were implemented on FPGA. The SRFFT design in [6] focuses on achieving scalability and high-throughput.…”

mentioning

confidence: 99%

Low‐complexity, energy‐efficient fully parallel split‐radix FFT architecture

Hazarika

Ahamed

Nemade

2022

Electronics Letters

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Fully parallel pipelined fast Fourier transform offers the highest throughput but requires high area and power. In this work, an efficient fast Fourier transform processor based on the split-radix algorithm is presented to reduce the hardware complexity of fully parallel fast Fourier transforms. In fully parallel pipelined implementations, splitradix fast Fourier transform requires considerably more registers compared to other fast Fourier transform algorithms leading to more power consumption and high latency in spite of having the least number of multiplications among all fast Fourier transforms. To address this issue, the authors present a new data-flow graph with no non-trivial twiddle factors in the odd stages of the split-radix fast Fourier transform. This facilitates significant reduction in the number of pipelining registers and a lower latency is achieved. Further, an efficient shift-add twiddle factor multiplier is proposed based on architectural analysis and substructure sharing. A comparison of the proposed design with existing fully parallel fast Fourier transforms is carried out and it is found that the proposed method outperforms other designs. Synthesis results show that the proposed design offers 45-57% area savings and 67-74% energy savings compared to the best existing fully parallel fast Fourier transform design.Data availability statement: Data available upon reasonable request.

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Design and Implementation of 256-Point Radix-4 100 Gbit/s FFT Algorithm into FPGA for High-Speed Applications

Cited by 20 publications

References 5 publications

Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G

Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G

Design of Spectrum Processing Chiplet Based on FFT Algorithm

Low‐complexity, energy‐efficient fully parallel split‐radix FFT architecture

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