Design and implementation of 4-bit ripple carry adder using SETMOS architecture

A novel pipelined carry adder design based on half adder

“…The critical path delay is determined by the longest pathway through the adder circuit. Therefore, the critical path delay of N-bit adders is determined by three gate delays of the first bit adder and to ripples in two gate delays of each of the next adders [1], explaining why it is called 'ripple carry adder (RCA)' [2], [3]. The critical path delay is calculated using (1).…”

“…(2) declares how the path delay requires multi-bit OR-AND gates to achieve the correct carry-out value.𝐶 𝑜𝑢𝑡 = 𝑔7 + 𝑝 7 𝑔 6 + 𝑝 7 𝑝 6 𝑔 5 + 𝑝 7 𝑝 6 𝑝 5 𝑔 4 + 𝑝 7 𝑝 6 𝑝 5 𝑝 4 𝑔 3 + 𝑝 7 𝑝 6 𝑝 5 𝑝 4 𝑝 3 𝑔 2 + 𝑝 7 𝑝 6 𝑝 5 𝑝 4 𝑝 3 𝑝 2 𝑔 1 + 𝑝 7 𝑝 6 𝑝 5 𝑝 4 𝑝 3 𝑝 2 𝑝 1 𝑔 0 + 𝑝 7 𝑝 6 𝑝 5 𝑝 4 𝑝 3 𝑝 2 𝑝 1 𝑝 0 𝐶 0…”