2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI) 2017
DOI: 10.1109/icacci.2017.8126126
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Design and implementation of 8-bit vedic multiplier using mGDI technique

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Cited by 9 publications
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“…As the wireless communicated signals are usually in-phase and quadrate-phase (I/Q) sampled, the multiplications and additions are both performed separately with its real and imaginary parts. According to [16], an 8-bit multiplier costs 748 transistors, and an 8-bit full adder requires 10 transistors. So that each 8-bit flops requires 1506 transistors.…”
Section: Numerical Experimentsmentioning
confidence: 99%
“…As the wireless communicated signals are usually in-phase and quadrate-phase (I/Q) sampled, the multiplications and additions are both performed separately with its real and imaginary parts. According to [16], an 8-bit multiplier costs 748 transistors, and an 8-bit full adder requires 10 transistors. So that each 8-bit flops requires 1506 transistors.…”
Section: Numerical Experimentsmentioning
confidence: 99%