Design and implementation of a low cost test bench to assess the reliability of FPGA

Naouss, Mohammad; Fabert, Marc

doi:10.1016/j.microrel.2015.06.087

Cited by 16 publications

(14 citation statements)

References 4 publications

(2 reference statements)

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“…In order to determine the most stable ring oscillator, four types of ring oscillator, which are 3 stages [24, 45, 46], 9 stages [47], 11 stages [48, 49] and 23 stages [32, 50] are simulated using Eldo simulator with ageing up to 10 years. All simulation results are shown in Figs.…”

Section: Methodsmentioning

confidence: 99%

“…The ring oscillator is continuously oscillating as long as the enable input is on. In this work, the ring oscillator uses the enable input switch [32, 48, 49, 53] instead of the reset input [50, 54], since the reset input causes the FPGA to reboot the entire system. If the enable switch is used as the input, the entire system is not affected as long as the digital temperature sensor is under an off condition.…”

Section: Methodsmentioning

confidence: 99%

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Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

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Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100°C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

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show abstract

“…2) Test Configuration: In the gate-level model, the delay change is used as the metric to capture the effect of wearout, thus the same metric is also used in the experimental part. We choose a ring oscillator (RO) structure which is widely used as a test platform [41] to measure the delay of the Circuit Under Test (CUT) to capture the delay change. Fig.…”

Section: A Gate-level Analytical Model For Accelerated and Active Rementioning

confidence: 99%

Implications of accelerated self-healing as a key design knob for cross-layer resilience

Guo

Stan

2017

Integration

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In this paper we propose a cross-layer accelerated self-healing (CLASH) system which "repairs" its wearout issues in a physical sense through accelerated and active recovery, by which wearout can be reversed while actively applying several accelerated self-healing techniques, such as high temperature and negative voltages. Different from previous solutions of coping with wearout issues (e.g. BTI) by "tolerating", "slowing down" or "compensating", which still leave the irreversible (permanent) wearout component unchecked, the proposed solution is able to fully avoid the irreversible wearout through periodic rejuvenation, and this is inspired by the explored frequency dependent behaviors of wearout and (accelerated and active) recovery based on measurements on FPGAs. We demonstrate a case where the chip can always be brought back to the fresh status by employing a pattern of 31-hour regular operation (under room temperature and nominal voltage) followed by a 1-hour accelerated selfhealing (under high temperature and negative voltage). The proposed system integrates the notions of accelerated self-healing across multiple layers of the system stack. At the circuit level, a negative voltage generator and heating elements are designed and implemented; at the architecture level, the core can be allocated in a way such that the dark silicon or redundant resources can be healed by active elements; at the system level, right balance of stress and accelerated/active recovery can be employed by the system scheduler to fully mitigate the wearout; various wearout sensors act as the media between different layers. Overall, these techniques work together to guarantee that the whole system performs for more of the time at higher levels of performance and power efficiency by fully taking advantage of the extra opportunities enabled by the accelerated self-healing.

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“…Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the continuous scaling of devices to deep nanotechnology and the inexorable reduction in supply voltage significantly challenge the reliability assurance that is related to device aging [1][2][3]. Aging results in FPGA performance degradation over time and, ultimately, hard faults.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Huang

Wang

et al. 2022

Sensors

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Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has become more significant with the sharp reduction in the process size of FPGAs. Aging results in FPGA performance degradation over time and, ultimately, hard faults. However, few studies have focused on understanding aging mechanisms or estimating the aging trend of 28-nm FPGAs. For this, we used a ring oscillator (RO)-based test structure to extract data and build a dataset that could be used to predict aging trends and determine the primary aging mechanisms of 28-nm FPGAs. Moreover, we proposed a correction method to correct temperature-induced measurement errors in accelerated tests. Furthermore, we employed four machine learning (ML) technologies that were based on accurate measurement datasets to predict FPGA aging trends. In the experiment, 24 XILINX 7-series FPGAs (28 nm) were evaluated for 10+ years of circuit operation using accelerated tests. The results showed that the aging effects of negative-bias temperature instability (NBTI) was the primary aging mechanism. The correction method proposed in this paper could effectively eliminate measurement errors. In addition, the minimum prediction error rate of the ML model was only 0.292%.

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Design and implementation of a low cost test bench to assess the reliability of FPGA

Cited by 16 publications

References 4 publications

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Implications of accelerated self-healing as a key design knob for cross-layer resilience

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

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