Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

Lin, Tay-Jyi; Chen, Shin-Kai; Kuo, Yu‐Ting; Li, Youfu; Hsiao, Pi-Chen

doi:10.1007/s11265-007-0061-x

Cited by 16 publications

(14 citation statements)

References 14 publications

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“…Figure 2 distributed & ping-pong register file, which supports highbandwidth data operands to and from the parallel functional units. Compared with an equivalent centralized register file used in state-of-the-art high-performance VLIW processors, the distributed & ping-pong register file reduces 76.8% silicon area and shortens 46.9% access times [3,8,9]. Table 1 summarizes the performance comparison of licensable cores for digital signal processing [10].…”

Section: Pacdsp Corementioning

confidence: 99%

“…However, PACDSP has a low-complexity register file instead of a centralized one in the other two DSP cores, and it still has the outstanding performance for its customized instructions and optimized program flow mechanisms. By the way, PACDSP has very high code density through its variable-length operation encoding, NOP removal, and embedded code replication techniques [3,11,12]. The program sequencer dynamically aligns the VLIW packets with different numbers of operations, each of which is itself variable-length encoded.…”

Section: Pacdsp Corementioning

confidence: 99%

“…The PAC project [1][2][3] was initiated in 2003 and executed by Industrial Technology Research Institute (ITRI) [4] in Taiwan, of which the target is to provide a fully-programmable solution for next-generation media-rich and multi-function portable devices, such as portable media players and smart phones. The speech, audio, image and video processing on these devices demand extremely high computing power under tight power constraints.…”

Section: Introductionmentioning

confidence: 99%

“…Very long instruction word (VLIW) architectures are the mainstreams of high-performance and energy-efficient designs [7], but they have serious drawbacks both on their register complexity and code density. A VLIW DSP (PACDSP) has been developed in the PAC project [3], of which the innovative distributed & ping-pong register file and variable-length VLIW encoding overcome the VLIW problems. A dual-core PAC SoC, which is composed of a PACDSP core, an ARM9 core and various on-chip peripherals, has been designed with dynamic voltage and frequency scaling (DVFS) capability.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

Chang

Lin

et al. 2010

J Sign Process Syst

Self Cite

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In order to develop a low-power and highperformance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. AVLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dualcore PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).

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Section: Pacdsp Corementioning

confidence: 99%

Section: Pacdsp Corementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

Chang

Lin

et al. 2010

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

show abstract

“…Different architectural design solutions [6] were proposed to increase performance and reduce power consumption. These solutions include DSPs, GPUs, VLIWs, and ASIPs combined with a myriad of techniques, e.g., loop transformations, software pipelining, and compiler optimizations [2,24,26].…”

Section: Introductionmentioning

confidence: 99%

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Ferreira

Denver

Pereira

et al. 2015

J Sign Process Syst

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In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code onthe-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated R. Ferreira ( ) · W. Denver that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.

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Compiler supports for VLIW DSP processors with SIMD intrinsics

Kuan

Lee

2011

Concurrency and Computation

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SUMMARYTo sustain growing multimedia workload, modern digital signal processing (DSP) processors are commonly equipped with subword instructions to accelerate signal processing. Besides subword, functional units of very long instruction word (VLIW) DSP processors can also be employed to process multiple data streams in parallel. However, because of power and area concerns, many embedded VLIW DSP processors adopt distributed register files to reduce read/write ports and wire connection by privatizing register files for clusters and even for functional units. The distributed design presents great challenges to compilers in distributing single instruction, multiple data (SIMD) workload to functional units. In this paper, we address the issue in supporting SIMD parallelism on VLIW DSP processors with subword instructions and distributed register files. Currently, industrial practices have adopted intrinsics that enable developers to utilize hardware resources and compete with hand-coded assembly in performance. However, it is still an open issue to provide such a solution for VLIW DSP processors with distributed register files. In this work, we provide SIMD intrinsics to allow programmers to write highly optimized codes by following given programming guides. In addition, an enhanced register allocation scheme and data replication optimizations are devised to enable efficient code generation. In our experiments, DSPstone benchmark and a set of H.264 kernels are used to evaluate the proposed programming and optimization schemes. The result shows that by combining SIMD intrinsics and compiler optimizations, one is able to obtain remarkable performance improvements, speedups of 2.9 and 3.5 for DSPstone and H.264 kernels, respectively.

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Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

Cited by 16 publications

References 14 publications

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Compiler supports for VLIW DSP processors with SIMD intrinsics

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