Design and Implementation of a CMOS 1Gsps 5bit Flash ADC with Offset Calibration

Li, Shiwen; Dang, Hua; Gao, Peng; Gui, Xiaoyan; Chen, Zhiming; Wang, Xinghua; Zhong, Shun‐Shi

doi:10.1109/greencom-ithings-cpscom.2013.339

Cited by 4 publications

(1 citation statement)

References 3 publications

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“…In [6], the offset was calibrated by current trimming using a current digital-to-analog converter (DAC). However, since a current DAC was required for each comparator, the total power consumption increased.…”

Section: Introductionmentioning

confidence: 99%

500 MS/s 4-Bit Flash ADC with Complementary Architecture

Lee,

Song,

et al. 2024

J. Electromagn. Eng. Sci

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This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 V<sub>pp</sub> operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and preamp circuits corresponding to the analog stages are designed using complementary architecture to attain a sufficient swing range even at a low supply voltage. Notably, the proposed structure satisfies the error requirements. The error source of the flash ADC, such as the comparator’s input referred offset, did not degrade its performance, while the use of a calibration circuit, characterized by power consumption and area burdens and increased complexity, could also be avoided. Therefore, the proposed flash ADC met the error requirements, such as the comparator’s input referred offset, without the need for calibration circuits. The chip, fabricated using the TSMC 65 nm process, covers an area of 1,160 × 950 μm<sup>2</sup> and consumes 78 mW of power. Furthermore, its signal-to-noise and distortion ratio and spurious-free dynamic range were measured to be 23.36 dB and 30.26 dB, respectively, at a sampling frequency of 500 MHz.

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Section: Introductionmentioning

confidence: 99%