Design and Implementation of AES using Hybrid Approach

Drsouza, Flevina Jonese; Panchal, Dakshata

doi:10.1109/peeic.2018.8665586

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…Among the fierce hacking attacks is the one that depends on attempting as many keys as possible to illegally access a message. The AES has offered a replacement of the data encryption standard (DES), as the AES was developed for avoiding the drawbacks of the DES [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Hassan¹,

Hamza²

2021

IJEECS

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<span>The data encryption is one of the most critical issues in the communication system design. Nowadays, many encryption algorithms are being updated to keep pace with the remarkable progress in the communication field. The advanced encryption standard (AES) is a common algorithm that has proved its efficacy. The main drawback of AES is that it uses too simple algebraic structures, since every block is always encrypted in the same way that makes the hacking process possible if the hacker captures the key and the uses S-Box in the input stage. This especially applies to the unwired communication systems where chances of hacking exceed those found in the wired systems. The paper proposes a security enhancement method that is based on utilizing concatenated AES and international data encryption algorithm (IDEA) algorithms. Upon applying the proposed algorithm, the hacking process becomes a great challenge. The paper incorporates the real-time FPGA implementation of the proposed algorithm in the encryption and the decryption stages. Besides, the paper presents a clear analysis of the system’s performance.</span>

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Section: Introductionmentioning

confidence: 99%

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Hassan¹,

Hamza²

2021

IJEECS

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“…The more time the encryption system takes to encrypt the data, the more chances increase for the hackers to break into the system [17,18]. This paper discusses the design, analysis and implementation of pipelined method to reduce the consumed numbers of clocks and speed up the processes [19].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Pipelined AES Encryption System using FPGA

Nabil¹,

Khalaf²,

Hassan³

2020

IJRTE

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Nowadays, the data encryption became very important because of the usage of the data transmission in all the filed. The Advanced Encryption Standard (AES) that known as Rijndael algorithm is one of the most common encryption algorithms. The AES consists of 9 rounds in addition to the initial and final rounds that makes the AES consumes much time for encrypting the data. Of course the time consumption is considered one of the problems that face the information security. The more time the encryption system consumes to encrypt the data, the more chances increase for the hackers to break into the system. In this work, we find a new technique that can be used to increase the performance speed of the advanced encryption standard. The proposed algorithm methodology depends on the pipelined processing method for the processing time reduction. The paper includes a discussion of the design, the analysis and the implementation using Field Programmable Gate Array (FPGA) of the pipelined method to reduce the consumed numbers of clocks and speed up the processes. The AES is used to protect information and encrypt sensitive data and used in satellites, missiles, military application and other critical application. The paper describes the AES encryption system algorithm and the implementation of both the normal processing and the pipelined processing, and finally a comparison between the two algorithms.

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