Design and Implementation of an Efficient LFSR using 2-PASCL and Reversible Logic Gates

Reddy, B. Naresh Kumar; Reddy, G. Sai Vishal; Vani, B. Veena

doi:10.1109/ibssc51096.2020.9332213

Cited by 7 publications

(1 citation statement)

References 19 publications

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“…https://www.indjst.org/ Figure 7 illustrates the delay and power analysis of the proposed design with existing literature. The critical delay in the proposed design is reduced by 67.56%, 81.75%, 90.94%, 91.87%, 93% and 95.06% when compared with LFSRs using bitswapping technique (13) , fuzzy logic (14) , reversible logic (15) , m-GDI logic (16) , GDI logic (16) and conventional CMOS logic (16) . In the same way, power is also reduced by 9.8%, 43.9%, and 61.6% in proposed LFSR when compared to the m-GDI, GDI and CMOS based LFSRs presented in articles (16,17) and (4) respectively.…”

Section: Resultsmentioning

confidence: 99%

Design, Implementation and Performance Analysis of Test Pattern Generator for Built-In Self-Test using m-GDI Technology

Kumar¹,

Kariyappa²,

Kurian³

2021

IJST

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Background: A Linear Feedback Shift Register (LFSR) is typically used for generating the test patterns in built-in self-test (BIST) as it produces pseudorandom patterns at every clock cycle. These pseudo-random patterns are used as test vectors for testing the VLSI circuits. Objective: The pseudorandom patterns generated by the LFSR exhibit low-correlation among the patterns, this increases the switching activity and power dissipation while testing the VLSI circuit. Thus, to reduce the testing power, modified gate diffusion input (m-GDI) logic based LFSR in 45nm technology is proposed in this paper. Methods: The circuits are developed on m-GDI technology using the Cadence virtuoso tool and a spectre simulator is used to carry out the simulation. Findings: Comparative analysis revealed that the delay and power are reduced significantly, for the proposed design when compared to the existing LFSRs in conventional CMOS, GDI and reversible logic. Novelty and applications: In conventional LFSR, an external source is necessary to load the seed value and it dissipates more power. But in the proposed design, the seed value is generated by the circuit itself. This reduces the power and critical path delay. Further a complete zero patterns is not possible in conventional LFSR design. But in proposed design, all zero pattern is plausible. The design obtained from this study can be applied in low-power, high-speed BIST circuits.

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