Design and Implementation of Boundary-Scan Circuit for FPGA

Xie, Xiaodong; Li, P.; Ruan, Anbang; Li, W. C.; Li, W.

doi:10.1109/cas-ictd.2009.4960798

Cited by 3 publications

(6 citation statements)

References 2 publications

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“…When boundary scan cells are connected in a chain, it forms boundary scan register [1]. Standard Boundary Scan Cell is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Boundary Scan cell is the basic building block of boundary scan test architecture through which Inputs/Outputs (I/Os) of the device under test are easily controllable and observable [5,6,7]. The Boundary Scan architecture is shown in Fig.1 [1].…”

Section: Introductionmentioning

confidence: 99%

“…Testing of PCB is essential to test the interconnections and components mounted on it [1,2]. In the mid of 1970's, the testing of boards were carried out with in-circuit testing.…”

Section: Introductionmentioning

confidence: 99%

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A novel method for diagnosis of board level interconnect faults using boundary scan

Kumar

Sharma

et al. 2010

2010 International Conference on Computer and Communication Technology (ICCCT)

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Over the past years complexity of PCB board and the surface mount technology has increased by leaps and bounds. This limits the use of traditional in-circuit test techniques for testing of such boards. This paper addresses the various issues of board level interconnect testing using Boundary Scan architecture. This work implements BIST using Boundary Scan technique. A new Algorithm is developed to diagnose PCB level faults. The dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults are taken up in this paper. The proposed algorithm is also compared with the existing algorithms viz modified counting, walking one's algorithm and others. Our results are found to be better than the existing algorithms.

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“…When boundary scan cells are connected in a chain, it forms boundary scan register [1]. Standard Boundary Scan Cell is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A novel method for diagnosis of board level interconnect faults using boundary scan

Kumar

Sharma

et al. 2010

2010 International Conference on Computer and Communication Technology (ICCCT)

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“…When BSCs are connected in a chain, it forms boundary scan register (Xie et al, 2009). Standard input and output BSCs are shown in Figures 2 and 3, respectively, (Setty and Martin, 1991).…”

Section: Introductionmentioning

confidence: 99%

“…In the age of modern electronics, the use of multilayered high-speed printed circuit boards (PCBs) has become a common practice in sophisticated equipments. So, testing of PCB is essential to test the interconnections and components mounted on it (Xie et al, 2009;Burgess et al, 1995;Mucha, 1996). In 1960s, testing was done manually.…”

Section: Introductionmentioning

confidence: 99%

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Sharma¹,

Sharma

Kaushik

et al. 2011

Circuit World

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Purpose -This paper aims to address the various issues of board-level (off-chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off-chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach -The problems in board-level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board-level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings -The dominant-1 (wired-OR, denoted as WOR), dominant-0 (wired-AND, denoted as WAND) and stuck-at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms.Research limitations/implications -The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications -The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value -Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board-level dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.

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Design and implementation of a standard cell based programmable logic core

Xie

Ruan

et al. 2009

2009 International Conference on Communications, Circuits and Systems

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Design and Implementation of Boundary-Scan Circuit for FPGA

Cited by 3 publications

References 2 publications

A novel method for diagnosis of board level interconnect faults using boundary scan

A novel method for diagnosis of board level interconnect faults using boundary scan

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Design and implementation of a standard cell based programmable logic core

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