2019
DOI: 10.1155/2019/9601961
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Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Abstract: In recent years, the increasing disparity between the data access speed of cache and processing speeds of processors has caused a major bottleneck in achieving high-performance 2-dimensional (2D) data processing, such as that in scientific computing and image processing. To solve this problem, this paper proposes new dual unit tile/line access cache memory based on a hierarchical hybrid Z-ordering data layout and multibank cache organization supporting skewed storage schemes. The proposed layout improves 2D da… Show more

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