2009 First International Conference on Information Science and Engineering 2009
DOI: 10.1109/icise.2009.461
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Design and Implementation of Digital Channelized Receiver in Multi-FPGA

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Cited by 11 publications
(4 citation statements)
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“…The output SNR is improved approximately times. Finally, the channelization receiver can be implemented in a parallel processing architecture, consequently it is able to tackle real-time processing on hardware platforms [ 29 , 30 ]. In virtue of these advantages, the proposed channelization-based method shows a better performance over the conventional ISM and TOPS methods.…”
Section: The Proposed Methodsmentioning
confidence: 99%
“…The output SNR is improved approximately times. Finally, the channelization receiver can be implemented in a parallel processing architecture, consequently it is able to tackle real-time processing on hardware platforms [ 29 , 30 ]. In virtue of these advantages, the proposed channelization-based method shows a better performance over the conventional ISM and TOPS methods.…”
Section: The Proposed Methodsmentioning
confidence: 99%
“…The non-ideal characteristics of the finite order lowpass filter cause the monitor blind spots between adjacent channels, which will result in the loss of signals. A method to avoid this effect is to make the passband of the lowpass filter cover the entire channel and allow the transitional band to extend to adjacent channels [3]. Taking four subchannels for example, the frequency division of the whole coverage band is shown in Fig.…”
Section: Lowpass Filter and Decimationmentioning
confidence: 99%
“…When α = π/2, the architecture of the channelized receiver shown in Fig. 4 becomes the architecture in the Fourier domain as described in [3]. So the architecture of the channelized receiver in the FRFD can be regarded as a generalization of that in the traditional Fourier domain.…”
Section: Channelized Implementation Based On Polyphase Filter For The...mentioning
confidence: 99%
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