Design and Implementation of Double Precision Floating Point Comparator

Antony, P Rony; Joseph, Anjana Mary

doi:10.1016/j.protcy.2016.08.141

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Cited by 3 publications

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Design of Double Precision Floating Point Comparator for Multiple Numbers

Chopde,

Daigavhane,

Damle

2024

Lecture Notes in Electrical Engineering

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Design of Double Precision Floating Point Comparator for Multiple Numbers

Chopde,

Daigavhane,

Damle

2024

Lecture Notes in Electrical Engineering

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Adaptive Single-layer Aggregation Framework for Energy-efficient and Privacy-preserving Load Forecasting in Heterogeneous Federated Smart Grids

Manzoor,

Jafri,

Zoha

2024

Internet of Things

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Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation

Saxena

Vudadha

2023

J CIRCUIT SYST COMP

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This paper presents the realization of binary and floating-point comparators on FPGA. The implementation is done by exploiting the primitive instantiation of FPGA resources which has enabled a significant improvement in resource utilization in terms of Look-Up Table (LUT) usage and overall combinational path delay when compared to the conventional inference approach. The comparator architectures are implemented using Vivado 2020.1 and ISE Design Suite 14.7 environment on multiple Xilinx FPGA platforms and are compared with the existing designs. The results indicate an improvement of 33.33% and 45.45% in LUT utilization, 14.41% and 30.73% in delay for 32-bit and 64-bit binary comparators respectively, compared to the existing architectures. The proposed floating-point comparator requires 88.57% and 285.29% lesser LUTs for single precision and double precision representation respectively, compared to the existing design.

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Design and Implementation of Double Precision Floating Point Comparator

Cited by 3 publications

References 6 publications

Design of Double Precision Floating Point Comparator for Multiple Numbers

Design of Double Precision Floating Point Comparator for Multiple Numbers

Adaptive Single-layer Aggregation Framework for Energy-efficient and Privacy-preserving Load Forecasting in Heterogeneous Federated Smart Grids

Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation

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