Design and implementation of flexible Numerical Overcurrent Relay on FPGA

Mitra, Subhrajit; Chattopadhyay, Paramita

doi:10.1016/j.ijepes.2018.07.022

Cited by 10 publications

(5 citation statements)

References 13 publications

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“…Salah satu cara alternatif yang dapat dilakukan untuk mengatasi permasalahan tersebut, yaitu dengan menerapkan arsitektur ADC multi kanal simultan. Dimana seluruh kanal ADC dapat melakukan proses sampling dan konversi dalam waktu yang bersamaan, dan hanya cukup satu intruksi saja yang dieksekusi oleh mikroprosessor untuk menjalankan proses sampling dan konversi pada seluruh kanal (Mitra & Chattopadhyay, 2019). Selain itu, penggunaan ADC multi kanal simultan dapat diimplementasikan untuk membentuk sistem pengukuran simultan.…”

Section: Pendahuluanunclassified

“…FPGA merupakan IC (Integrated Circuit) yang di dalamnya terdapat jutaan gerbang transistor terprogram yang dapat dikonfigurasi dan dibangun menjadi rangkaian gerbang logika dasar dan juga beberapa rangkaian logika digital kombinasional. FPGA juga dapat dikembangkan sebagai pemroses sinyal digital (DSP) (Mitra & Chattopadhyay, 2019). Di dalam IC FPGA terdapat fitur Digital Clock Manager (DCM), sehingga dapat dibangun beberapa arsitektur rangkaian digital yang dapat bekerja secara parallel dan simultan (Zet & Fosalau, 2019).…”

Section: Pendahuluanunclassified

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Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10

NUHA

DHARMAWAN²,

SAKTI³

2022

ELKOMIKA

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ABSTRAKDesain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan. Paper ini memaparkan desain ADC SAR (Successive Approximation Register) 10-bit dua kanal simultan menggunakan Board FPGA (Field Programmable Gate Array) Altera DE10. FPGA dikonfigurasi untuk difungsikan sebagai sirkuit logika SAR dua kanal menggunakan bahasa VHDL (VHSIC-Very High Speed Integrated Circuit Hardware Description Language). Hasil pengujian menunjukkan kanal ADC_1 dan ADC_2 memiliki tingkat kesalahan rata-rata sebesar 1.05 % dan 0.90 %, tingkat akurasi sebesar 98.95 % dan 99.09 %, tingkat linearitas dengan koefisien korelasi sebesar 0.9999 dan 0.9999. Durasi waktu yang dibutuhkan dalam satu kali proses konversi ADC yaitu 104 μs. Didapatkan sampling-rate sebesar 9.6 KS/s. Daya yang dikonsumsi sebesar 842 mW. Kedua kanal ADC SAR yang telah dibuat mampu bekerja secara simultan.Kata kunci: ADC, dua-kanal simultan, FPGA, SAR, VHDL ABSTRACTDesing of simultaneous multi-channel ADC (Analog to Digital Converter) architecture on the controller device can reduce the number of program instructions (tasks) that must be executed by microprocessor and can be used to form simultaneous measurements. This paper describes design of simultaneous two channel 10-bit SAR (Successive Approximation Register) ADC by using Board FPGA (Field Programmable Gate Array) Altera DE10. FPGA is configured using VHDL (VHSIC-Very High Speed Integrated Circuit Hardware Description Language) language to function as two channels SAR logic circuit. Test results show that ADC_1 and ADC_2 channels have average error of 1.05% and 0.90%, accuracy of 98.95% and 99.09%, linearity level with correlation coefficient of 0.9999 and 0.9999. Time duration in one ADC conversion process is 104 μs. The sampling rate obtained is 9.6 KS/s. Power consumed is 842 mW. Design of two channels SAR ADC that has been made can work simultaneously.Keywords: ADC, two-channels simultaneous, FPGA, SAR, VHDL

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Section: Pendahuluanunclassified

Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10

NUHA

DHARMAWAN²,

SAKTI³

2022

ELKOMIKA

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“…Researchers have optimized overcurrent relays using FPGA technology for high-speed protective relays in smart grids [ 18 , 19 , 20 , 21 ]. In [ 18 ], an ANN-based flexible over-current relay on an FPGA achieves an ultra-low processing time and adaptive remote settings. Ref.…”

Section: Introductionmentioning

confidence: 99%

Field Programmable Gate Array-Based Smart Switch to Avoid Inrush Current in PV Installations

Martínez-Figueroa,

Córcoles,

Bogarra

2024

Sensors

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This paper introduces an FPGA-based implementation of a smart switch designed to avoid inrush currents occurring during the connection of single-phase transformers utilized in grid-connected photovoltaic (PV) systems. The magnitude of inrush currents is notably impacted by the residual flux within the transformer core and the precise moment of energization relative to the wave cycle. Alternative methods frequently hinge on intricate procedures to estimate residual flux. This challenge is adeptly circumvented by the innovative smart control system proposed herein, rendering it a cost-effective solution for grid-connected PV systems. The proposed solution for mitigating inrush current remains effective, even in the face of challenges with current and voltage sensors. This resilience arises from the system’s ability to learn and adapt by leveraging information acquired from the network.

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“…FPGA's have many desired characteristics when it comes to digital power protection, like its configurable logical blocks, natural parallel hardwired architecture, low computational latency while interfacing with peripherals, and high processing power and speed. These attributes are explored by and Dinavahi (2016), who proposed a multifunctional protective relay realtime system in a Virtex-7 Xilinx® device, and Mitra and Chattopadhyay (2019), who developed an adaptive overcurrent protection function for distributed generation systems using an Artificial Neural Network (ANN), embedded in a Cyclone IV Intel® device. Both works show the capabilities of this class of devices for power protection systems, by delivering a trip time close to the characteristic equation of those functions, with little delay.…”

Section: Introductionmentioning

confidence: 99%

“…One type of platform that may have those features are singleboard computers. Since little is known about their application in power protection systems, this paper investigates the possibility of a particular single-board computer, a Raspberry Pi 3B+, to be utilized as a dedicated real-time system for power protection applications, from simple power protection functions, like an overcurrent function to detect symmetrical three-phase faults, to more complex power protection algorithms, like the ones based on machine learning techniques (Mitra and Chattopadhyay, 2019;Monaro, 2013). The main goal of this application is to provide a low-cost solution for other researchers to quickly implement and test their own novel power protection algorithms in hardware.…”

Section: Introductionmentioning

confidence: 99%

Development of a Low-Cost Relay Prototype for Real-Time Power Protection Functions

Lopes¹,

Bertho²

2023

Learn. Nonlin. Mod.

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This paper presents a Raspberry Pi 3B+ based low-cost universal relay able to run power protection functions in real-time. The configurations necessary for this single-board computer to be able to provide real-time response are shown, as for latency tests to verify its response time. An experimental circuit was built to send three-phase fault signals from a Relay tester to the low-cost relay, in order to evaluate its response time to clear faults in comparison to a commercial relay. A neural networks algorithm was developed and executed in real-time by the proposed low-cost relay, which is able to differentiate three-phase faults from transient signals created from large load variations. The results show that the low-cost relay is capable of running simple and complex protection functions within a pre-defined runtime and acceptable precision, compared to a commercial protection relay. However, the sampling frequency the low-cost relay is able to handle is limited. The results have also shown that the low-cost relay meet the requirements for a soft real-time system, which is not ideal for practical power protection systems that require hard real-time systems.

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Design and implementation of flexible Numerical Overcurrent Relay on FPGA

Cited by 10 publications

References 13 publications

Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10

Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10

Field Programmable Gate Array-Based Smart Switch to Avoid Inrush Current in PV Installations

Development of a Low-Cost Relay Prototype for Real-Time Power Protection Functions

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