Design and implementation of floating point multiplier based on Vedic Multiplication Technique

Kanhe, Aniruddha; Das, Shishir Kumar; Singh, Ankit

doi:10.1109/iccict.2012.6398204

Cited by 24 publications

(7 citation statements)

References 2 publications

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“…A multiplier is one of the most important building block that is widely used in real-time Digital signal Processing (DSP). Multiplier block should be operated with low power, with minimized layout area while operating at high speed in real-time DSP processing task [4]. Now a days, the multiplier is implemented using both the CMOS [5], MCML logic styles [6] to improve the performance.…”

Section: Introductionmentioning

confidence: 99%

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Devi¹,

Bhanumathi²

2022

Computers, Materials &Amp; Continua

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Now a days, MOS Current Mode Logic (MCML) has emerged as a better alternative to Complementary Metal Oxide Semiconductor (CMOS) logic in digital circuits. Recent works have only traditional logic gates that have issues with information loss. Reversible logic is incorporated with MOS Current Mode Logic (MCML) in this proposed work to solve this problem, which is used for multiplier design, D Flip-Flop (DFF) and register. The minimization of power and area is the main aim of the work. In reversible logic, the count of outputs and inputs is retained as the same value for creating one-to-one mapping. A unique output vector set can be generated for each input vector set and information loss is also prevented. In reversible MCML based multiplier, reversible logic full adder is utilized to minimize the area and power. D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register. The proposed reversible MCML multiplier attains average power of 0.683 mW, Reversible MCML based DFF achieves 0.56 µW and Reversible MCML based 8-bit register attains 04.04 µW. The result shows that the proposed Reversible MCML based multiplier, Reversible MCML based D flip-flop and Reversible MCML based register achieves better performance in terms of current, power dissipation, average power and area.

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Section: Introductionmentioning

confidence: 99%

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Devi¹,

Bhanumathi²

2022

Computers, Materials &Amp; Continua

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“…The system design is coded using VHDL language and synthesized for FPGA products with XILLINX 13.1 software [11]. Moses et.al.have examined how the Vedic algorithm of Urdhva Tiryakbhyam speeds up the computation of his algorithm when compared with conventional algorithms in existence [12].Khanhe and his team have developed and implemented floating point multiplier based on Vedic Multiplication Technique [13]. In this paper efforts have been made to design and implement multiplier using both the algorithms array and UrdhvaTiryakbhyam Vedic Sutra.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Array Multiplier and Vedic Multiplier using Xilinx

Manikrao¹,

Shrikant²

2016

CAE

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Many important signal processing systems are designed on VLSI platform as the integration growing rapidly. The signal processing systems and applications requires large computation capacity and hence takes considerable amount of energy. In the VLSI system design performance and area are the two very important parameters. Generally performance of any system is determined by the performance of the element that is multiplier. Multiplier is the slow element in the system. The two terms the area and speed are the main hurdles before the researcher because to improve the speed results in large area. As a result, while designing of multiplier with optimised speed and area is the major challenge. Therefore design of low-power multiplier has been an important area in VLSI system design research. Many researchers have been worked at circuit and logic, technology, physical level on designing low power, low area multipliers. The present paper deals with design and implementation of efficient high speed 16x16 multiplier using various algorithms like array & booth, and using Vedic operators. Multipliers are compared on the basis of optimized area, speed and memory required.

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“…The high speed multiplier proposed in this paper exhibits improved speed. In [8], 8x8 Vedic multiplier is implemented using 4x4 multiplier which in turn is implemented using 2x2 multiplier blocks. It is implemented using Verilog HDL on Xilinx FPGA Spartan 3 board.…”

Section: Vedic Mathematicsmentioning

confidence: 99%

Light Weight Asymmetric Cryptographic Algorithm for Financial Transactions through Mobile Application

Maria¹,

Anitha²

2017

IJCA

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Nowadays world is seen through mobile internet in a fraction of seconds, which invaded the need for many mobile applications. Financial transactions through mobile phones has become primitive mode of transactions. All these mobile applications including financial transactions demands for better security due to pervasive environment. In our work, we propose light weight Elliptical Curve Cryptographic method suitable for mobile applications. Elliptic curve point multiplication or scalar multiplication is the operation of adding a point P on the elliptic curve to itself successively scalar number of times. This paper describes an algorithm for light weight computation of scalar multiplication for elliptic curves defined over binary fields using projective coordinate system eliminating the need to perform inversions as needed with computations involving affine coordinates. It effectively incorporates fast computation method for binary elliptic curves by making use of Exclusive-OR gates. The effectiveness of the algorithm is measured both by Matlab simulation and Field-Programmable Gate Array (FPGA) implementation. Hardware implementation using Verilog proves that the proposed algorithm consumes less resources in terms of delay and power.

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Design and implementation of floating point multiplier based on Vedic Multiplication Technique

Cited by 24 publications

References 2 publications

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Analysis of Array Multiplier and Vedic Multiplier using Xilinx

Light Weight Asymmetric Cryptographic Algorithm for Financial Transactions through Mobile Application

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