Design and Implementation of FPGA Based Dynamically Re-Configurable Processor for Machine Learning Systems

Bachanna, Prashant; Gadgay, Baswaraj

doi:10.1109/mysurucon52639.2021.9641553

Cited by 1 publication

(1 citation statement)

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“…Simulations obtained using synthetic traffic mixes and real benchmarks will exhibit that QORE will enhance the throughput by 2.3 GHz and speedup by 1.3 GHz compared with Vicis and Ariadne multi-processor with NoC designs known for fault-tolerant designs. By making use of a compiler such as synopsys design compiler our QORE design reduces the power consumption of the network by 21% with minimal control overhead [19]. During minimal traffic, this proposed router will have low latency and also allow the arriving packets to bypass effectively through these shared queues.…”

Section: Literature Surveymentioning

confidence: 99%

Optimization of re-configurable multi-core processors and security based on field programmable gate arrays

Bachanna,

Hari Sankar,

Kumar Tripath

et al. 2024

IJEECS

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<div align="center">n system-on-a-chip based complex processors has the problem of multithreading and miss-functionality due to their complexity and high-speed operations. In order to minimize these problems, the proposed design has machine learning based algorithms and cryptography systems for security has been incorporated. In the proposed work, the security level has been taken care of in three different stages such as data integrity, data authentication, and private and public keys encryption and decryption. In order to increase throughput with minimal latency, the proposed architecture with advanced high-performance protocol and advanced high-performance and advanced peripheral bus bridge is incorporated between the fabric dynamically re configurable multi-processor and peripherals along with security algorithms using secure hash algorithm (SHA-256) bits and advanced encryption standard (AES). In order to perform machine learning based applications, the proposed system is incorporated double-precision floating point arithmetic operations. The overall proposed architecture is developed in verilog hybrid deep learning (HDL) and quality checking using the LINT tool. The entire design is interfaced with the Zynq processor and software development kit (SDK) tool to verify data transfer between hardware and software. The obtained results are compared with existing state-of-art results and found that 18% improvement in throughput, a 21% improvement in power consumption savings, and a 34% reduction in latency.</div>

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Section: Literature Surveymentioning

confidence: 99%