Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

Abstract

: Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. The multiplication process requires more hardware resources and processing time when compared with addition and subtraction. This paper presents, Design and Implementation of FPGA based Complex Floating Point Multiplier using Combined Integer and Floating point Multiplier (CIFM). The Processing speed of the multipliers decides the execution time of the system as it consumes most of the time. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The architectures for the three multiplier solutions of complex multiplier for 32 x 32 bit complex numbers multiplication are coded in VHDL and implemented through Xilinx ISE 13.4 navigator and Modelsim 5.6 and their performance is compared. The complex floating point multiplication with single precision using CIFM multiplier has comparatively less amount of delay and power consumption with respect to Vedic and Array multiplier.