1991
DOI: 10.1148/radiology.179.2.2014312
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Design and implementation of full-frame, bit-allocation image-compression hardware module. Work in progress.

Abstract: A hardware module was designed and built to implement the full-frame, bit-allocation image-compression algorithm in a clinical setting. The algorithm transforms an entire image without prepartitioning into small subimages. This adaptation eliminates block artifacts at subimage borders that can mimic relevant pathologic conditions. The quality of 1,024- and 2,048-pixel images compressed at a rate up to 10:1 with a custom-designed processor board (which contains four digital signal processors that transform and … Show more

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Cited by 10 publications
(7 citation statements)
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“…5 This system has been used in studies detecting several diseases (such as subperiosteal resorption, interstitial lung disease, and pulmonary nodules). [6][7][8] For example, in detecting subtle pulmonary nodules, observer performance was equivalent for compressed and uncompressed images for a compression ratio up to 44.…”
Section: Compressionmentioning
confidence: 99%
“…5 This system has been used in studies detecting several diseases (such as subperiosteal resorption, interstitial lung disease, and pulmonary nodules). [6][7][8] For example, in detecting subtle pulmonary nodules, observer performance was equivalent for compressed and uncompressed images for a compression ratio up to 44.…”
Section: Compressionmentioning
confidence: 99%
“…The ratios are 20:1 for radiographs, 8:1 for CT, and 4:1 for MR images. Although, many compression methods are being used by various groups, these ratios are considered conservative and comparable in quality among the most prevalent types, including JPEG (Joint Photographic Experts' Group) [13], full frame DCT [14], and wavelet transform [15]. The compression ratios of CT and MR images can be further improved using a three dimensional wavelet transform method [16].…”
Section: Compressionmentioning
confidence: 99%
“…We developed a parallel processor hardware module [6,7,8] with four Motorola (Phoenix, AZ) DSP56001s (QDSP). This module is compatible with all models of Sun host computers with the VME backplane, including 3/E, 3/360, 4/E, 4/470 and 4/490.…”
Section: Ffdct and Hardware Modulementioning
confidence: 99%
“…We implemented this entire compression algorithm using parallel digital signal processors (DSP). Twenty four bits processors which met the dynamic range required for the large matrix transform just became available at the time our hardware implementation began.We developed a parallel processor hardware module [6,7,8] with four Motorola (Phoenix, AZ) DSP56001s (QDSP). This module is compatible with all models of Sun host computers with the VME backplane, including 3/E, 3/360, 4/E, 4/470 and 4/490.…”
mentioning
confidence: 99%
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