Design and implementation of high performance and area efficient square architecture using Vedic Mathematics

Reddy, B. Naresh Kumar

doi:10.1007/s10470-019-01496-w

Cited by 25 publications

(7 citation statements)

References 16 publications

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“…6. In table 4, the (-,-) combination, the delay was reduced by -, 23%, 55%, 45%, and 17% in proposed method-1 for various bit-widths, and in proposed method-2, it was reduced by 25%, 56%, 44%, 26%, for inference in the proposed method-3 was reduced by 7%, 53%, 60%, 44%, 27% and nally in proposed method-4 the results indicate that the delay was reduced by 4%, 53%, 63%, 43%, 27% [10].…”

Section: Resultsmentioning

confidence: 83%

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Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

Kalaiselvi,

Sabeenian

2024

Analog Integr Circ Sig Process

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Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employed to address challenging problems in recent studies. Various designs have been developed for the FPGA implementation employing VLSI design approaches and parallel computing technology. Signal processing, machine learning, and recon gurable computing research should be closely monitored as arti cial intelligence develops. To enable deep learning algorithms, continued research should be done on energy-constrained computing technology. Multipliers and adders are key components of deep learning algorithms. The multiplier is an energy-intensive component of signal processing in ALU, Convolutional Neural Networks (CNN), and Deep Neural Networks (DNN). For the DNN, this method introduces the Booth multiplier blocks and the carry-save multiplier in the Anurupyena architecture. Traditional multiplication methods like the array multiplier, Wallace multiplier, and Booth multiplier are contrasted with the Vedic mathematics algorithms. On a speci c hardware platform, Vedic algorithms perform faster, use less power, and take up less space. Implementations were carried out using Verilog HDL and Xilinx Vivado 2019.1 on Kintex-7. The area and propagation delay were reduced compared to other multiplier architectures.

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Section: Resultsmentioning

confidence: 83%

“…The complete architecture is branched into two parts to get the desired results and concatenated. The delay and four input LUTs were measured using the Xilinx Vivado tool [10].…”

Section: Related Workmentioning

confidence: 99%

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

Kalaiselvi,

Sabeenian

2024

Analog Integr Circ Sig Process

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“…The multiplier is small and requires less space based on Booth encoding, but the UT sutra increases speed 34 . Based on the anurupyena sutra of Vedic arithmetic, it uses a high-performance and area-efficient square architecture for variable bit operands 35 . The Spartan 6 FPGA implementation models the hybrid parallel adder-based multiplier, which is utilized to improve multiplier performance 36 .…”

Section: Related Workmentioning

confidence: 99%

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi,

Sabeenian

2023

Sci Rep

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A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to enhance the speed and reduction in the area by using two VLSI architectures of radix encoding techniques—Radix-4 and Radix-8—with the Vedic multiplier. The functionality of the proposed methods is tested using an Artix-7 Field Programmable Gate Array (FPGA-XC7A100T-CSG324) in Xilinx Vivado 2019.1 and ASIC 45 nm technology. Two methods of Booth encoding using Vedic multiplier (Urdhva-Tiryakbhyam sutra) were used to develop, and examine the benefits of rapid computational multiplier. The results of the proposed multiplier for Booth-Vedic-Radix-4 encoding (BVR-4) decrease area by 89% and improve Area-Delay Product (ADP) by 72% for a 16-bit multiplier when subjected to other existing multipliers. The Booth-Vedic-Radix-8 (BVR-8) method shows that there will be an 89% reduction in area and an improvement in ADP by 72% for the 16-bit multiplier. The performance is evaluated regarding area occupancy (i.e., LUTs number) and propagation delay (output time). In terms of resource utilization, the proposed BVR-4 and BVR-8 multipliers outperform all the current designs with a marginal effect on speed and area for narrower bit-width ranges.

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“…Vedic mathematical methods can be shown to be more efficient than traditional methods in FIR and IIR filters for producing effective outcomes in biomedical signal de-noising. Reddy [10] focuses on square architecture based on the Anurupya Sutra. Their proposed method is an efficient way for dividing a large magnitude number into smaller magnitude numbers and concatenating the smaller magnitude numbers.…”

Section: Application Of Vedic Mathematics In Modern Timementioning

confidence: 99%

An Overview of the Ancient Indian Vedic Mathematics Techniques

Kumari¹

2022

IJRASET

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This study examined at how Vedic Mathematics solves basic math problems using Vedic Mathematics. The ancient approach of Indian mathematics is known as Vedic mathematics. It employs a one-of-a-kind computation method based on the 16 sutras and 13 sub-sutras including a variety of modern mathematical problems such as trigonometry, arithmetic, geometry, factorization, quadratic equations, and calculus. This study summarizes some important sutras from Vedic mathematics with examples. Additionally, we highlight some recent applications of Vedic mathematics from existing literature.

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Design and implementation of high performance and area efficient square architecture using Vedic Mathematics

Cited by 25 publications

References 16 publications

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

An Overview of the Ancient Indian Vedic Mathematics Techniques

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