Design and Implementation of Low-Power IoT RISC-V Processor with Hybrid Encryption Accelerator

Abstract

The security and reliability of data transmission between IoT devices are considered to be major challenges in the development of IoT technology. This paper presents a low-power, low-cost RISC-V processor for IoT applications with an integrated hybrid encryption accelerator, which can achieve efficient and secure encryption and decryption of data transmitted between IoT devices. The hybrid encryption accelerator, which uses the SM3 and the SM4, respectively, as hash and symmetric encryption algorithms, achieves a balance between encryption security, high speed, and key-management convenience. Both the processor and encryption accelerator are designed using the Verilog HDL language and are subsequently implemented and evaluated on both FPGA and ASIC platforms. The performance of the proposed processor and that of the Hummingbird E203 and the XuanTie E902 are compared. It is shown that, on the FPGA platform, the total resource utilization rate is reduced by 39.1~66.2%. In a 90 nm CMOS process, it is shown that the power efficiency of the proposed processor is increased by 10~34.8% and the circuit area is reduced by 32.5~57.1%.

Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks

“…The predominant catalyst for this increased attention is the energy-efficient operation characteristic of these networks, as highlighted in [ 10 ]. This aspect distinguishes SNNs from traditional low-power techniques, as documented in various studies [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 ]. SNN models are inherently reactive to event-based data, making them particularly apt for address-event representation-based computations, as explored in [ 22 ].…”