Design and implementation of parallel CRC algorithm for fibre channel on FPGA

Chuxiong, Wu; Shi, Haifeng

doi:10.1049/joe.2019.0727

Cited by 2 publications

(1 citation statement)

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“…It can be configured for a different polynomial at any time externally. [23] introduces a design and development of parallel CRC algorithm for the hardware implementation on FPGA to meet the specifications for FC. The algorithm can process 128-bit parallel data in a block by broken it into four 32-bit data and calculate their CRC, respectively, based on the LFSR.…”

Section: B Comparison With More Workmentioning

confidence: 99%

Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

Liu¹,

Qiu²,

Pan³

et al. 2020

Preprint

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Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 81.7%-85.9% and 2.9%-20.8% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

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Section: B Comparison With More Workmentioning

confidence: 99%