Design and Implementation of RISC MIPS Processor on FPGA

Abstract

In this paper, the design and implementation of RISC Processor is proposed with MIPS (Microprocessor without interlocked pipelined stages) technique. This processor performs 16-bit operations using pipelined technique, to improve the performance. This processor performs arithmetic, logical and data movement operations, more efficiently in terms of delay and power. The processor is composed of five stages namely, instruction fetch, instruction decode, execute, memory access and write back. The proposed 16-bit RISC MIPS processor is designed using Verilog and validated using Modelism, it is synthesized using libraries of AMD 45nm technology in Xilinx tool and implemented on Xilinx Spartan 6 FPGA. The proposed RISC MIPS gives reduced overall delay of 3.565ns and overall power consumption of 0.014W.