Design and implementation of SET-CMOS hybrid half subtractor

Ghosh, Arpita; Jain, Amit; Singh, N. Basanta; Sarkar, Subir Kumar

doi:10.1109/indicon.2014.7030405

Cited by 8 publications

(3 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is possible to address the first two criteria listed above by using different nanodevices such as the carbon nanotube FET (CNFET) [2], resonant tunnel diode (RTD) [3], rapid single quantum flux (RSQF) devices [4], single-electron transistor (SET) [5][6][7][8], etc. The current work considers different potential nanoelectronic binary multiplier design based on the single-electron threshold logic gate (SE-TLG) [9][10][11][12], the hybrid SET-CMOS approach [13][14][15], and CNFET-based designs [16,17]. The results are also compared with the conventional CMOS-based implementation of the same.…”

Section: Introductionmentioning

confidence: 99%

The design and performance of different nanoelectronic binary multipliers

Ghosh¹,

Jain

Sarkar

2021

J Comput Electron

Self Cite

View full text Add to dashboard Cite

The design and performance of digital binary multipliers built using different types of nanoelectronic devices are investigated herein. Designs for 2 × 2 binary multipliers implemented using different technologies such as single-electron-threshold logic (SE-TLG), hybrid single-electron transistor/complementary metal-oxide-semiconductor (SET-CMOS), and carbon nanotube field-effect transistor (CNFET) devices are elaborated and presented with corresponding simulation results. The performance metrics considered for their comparison are the power consumption, the circuit area, the propagation delay, the operating temperature, the design platform, etc. The existing CMOS-based design is also compared with all three proposed designs. The comparative analysis indicates that the SE-TLG-based 2 × 2 binary multiplier design exhibits very low power consumption, the smallest area requirement, and the shortest propagation delay among the three. Meanwhile, the design based on hybrid SET-CMOS devices can operate at room temperature and delivers the optimal response in terms of all the other performance metrics when compared with the other circuit implementations considered herein. Further stability analysis of the designs based on SE-TLG and hybrid SET-CMOS devices is carried out to validate their performance.

show abstract

Section: Introductionmentioning

confidence: 99%

The design and performance of different nanoelectronic binary multipliers

Ghosh¹,

Jain

Sarkar

2021

J Comput Electron

Self Cite

View full text Add to dashboard Cite

show abstract

“…Clearly, the driving ability of SETs is insufficient for long-distance transmission, nor can they handle too much load. For this reason, hybrid SET-FET circuits have been used in several applications [22][23][24][25] due to the high driving ability of metal-oxide-semiconductor fieldeffect transistors (MOSFETs), providing an effective solution to the driving problem of SET-based neurons. However, a serious problem remains in ANN circuit designs, viz.…”

Section: Introductionmentioning

confidence: 99%

Memristive-synapse spiking neural networks based on single-electron transistors

Long

Zhang

2019

J Comput Electron

View full text Add to dashboard Cite

In recent decades, with the rapid development of artificial intelligence technologies and bionic engineering, the spiking neural network (SNN), inspired by biological neural systems, has become one of the most promising research topics, enjoying numerous applications in various fields. Due to its complex structure, the simplification of SNN circuits requires serious consideration, along with their power consumption and space occupation. In this regard, the use of SSN circuits based on single-electron transistors (SETs) and modified memristor synapses is proposed herein. A prominent feature of SETs is Coulomb oscillation, which has characteristics similar to the pulses produced by spiking neurons. Here, a novel window function is used in the memristor model to improve the linearity of the memristor and solve the boundary and terminal lock problems. In addition, we modify the memristor synapse to achieve better weight control. Finally, to test the SNN constructed with SETs and memristor synapses, an associative memory learning process, including memory construction, loss, reconstruction, and change, is implemented in the circuit using the PSPICE simulator.

show abstract

“…Hybrid circuits utilizing the features of SET and CMOS has been proposed by K.Uchida et al and S. J. Kim et al [10] , [11]. Design and simulation of hybrid digital logic circuit has also been reported in the literature [12], [13] [14].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of an asynchronous arbiter circuit using SET CMOS hybrid architecture approach

Dutta

Singh²,

Jain

et al. 2015

International Conference on Computing, Communication &Amp; Automation

Self Cite

View full text Add to dashboard Cite

This paper demonstrates a CMOS Single electron transistor (SET) hybrid arbiter circuit which will act like a communication switch between multiple resources. The proposed architecture combines the merits of CMOS and SET to give a more efficient and compact nanometer scale circuit. The designed arbiter circuit utilizes the Coulomb blockade oscillation characteristics of SET to give better performances in terms of circuit area, power dissipation and delay. MIB compact model and BSIM4.6 model is used to design the circuit and the functionality of the result is verified by Tanner spice simulator.

show abstract

Design and implementation of SET-CMOS hybrid half subtractor

Cited by 8 publications

References 5 publications

The design and performance of different nanoelectronic binary multipliers

The design and performance of different nanoelectronic binary multipliers

Memristive-synapse spiking neural networks based on single-electron transistors

Design and implementation of an asynchronous arbiter circuit using SET CMOS hybrid architecture approach

Contact Info

Product

Resources

About