Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata

Zhang, Yongqiang; Zhu, Chunsong; Cheng, Xin; Xie, Guangjun

doi:10.1109/tcsii.2022.3171848

Cited by 1 publication

(1 citation statement)

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“…However, it uses a lot of cells and has a large area. In addition, a variety of QCA circuits have been proposed, such as: full adders [34,35], memory cell [36][37][38], multi-bit full comparator [39] and other circuits [40][41][42][43][44][45]. Sequential logic elements have also been implemented in these QCA circuits.…”

Section: Introductionmentioning

confidence: 99%

Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata

Yan

Liu

et al. 2023

Electronics

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Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.

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