Design and implementation of the blue gene/P snoop filter

Salapura, Valentina; Blumrich, Matthias A.; Gara, Alan

doi:10.1109/hpca.2008.4658623

Cited by 29 publications

(22 citation statements)

References 18 publications

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“…Researchers at IBM introduced a Stream Register-based snoop filter, which was used in the Blue Gene/P supercomputer [6,16,17]. This filter is inclusive, and uses stream registers to encode cache blocks stored in the cache.…”

Section: Stream Register Snoop Filtersmentioning

confidence: 99%

“…One of the most effective snoop filter architectures is based on stream registers, which provide a compact set-based representation of a contiguous range of memory blocks [6,16,17]. Stream registers can track the blocks that are allocated to a cache, which allows them to act as snoop filters; however, there is no efficient method to update a stream register when a block is removed from the cache.…”

Section: Introductionmentioning

confidence: 99%

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Counting stream registers: An efficient and effective snoop filter architecture

Ranganathan

Bayrak

Kluter

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-We introduce a counting stream register snoop filter, which improves the performance of existing snoop filters based on stream registers. Over time, this class of snoop filters loses the ability to filter memory addresses that have been loaded, and then evicted, from the caches that are filtered; they include cache wrap detection logic, which resets the filter whenever the contents of the cache have been completely replaced. The counting stream register snoop filter introduced here replaces the cache wrap detection logic with a direct-mapped update unit and augments each stream register with a counter, which acts as a validity checker; loading new data into the cache increments the counter, while replacements, snoopy invalidations, and evictions decrement it. A cache wrap is detected whenever the counter reaches zero. Our experimental evaluation shows that the counting stream register snoop filter architecture improves the accuracy compared to traditional stream register snoop filters for representative embedded workloads.

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Section: Stream Register Snoop Filtersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Counting stream registers: An efficient and effective snoop filter architecture

Ranganathan

Bayrak

Kluter

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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“…Jetty [14] uses counting Bloom filters to represent the set of all blocks cached by a processor to reduce cache snoops. Blue Gene/P employs several filters to avoid unnecessary snoops [17]. Reducing the bandwidth of broadcast protocols improves the scability of bus-based systems.…”

Section: Related Workmentioning

confidence: 99%

SigNet: Network-on-chip filtering for coarse vector directories

Jerger¹

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-Scalable cache coherence is imperative as systems move into the many-core era with cores counts numbering in the hundreds. Directory protocols are often favored as more scalable in terms of bandwidth requirements than broadcast protocols; however, directories incur storage overheads that can become prohibitive with large systems. In this paper, we explore the impact that reducing directory overheads has on the network-on-chip and propose SigNet to mitigate these issues. SigNet utilizes signatures within the network fabric to filter out extraneous requests prior to reaching their destination. Overall, we demonstrate average reductions in interconnect activity of 21% and latency improvements of 20% over a coarse vector directory while utilizing as little as 25% of the area of a fullmap directory.

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“…Powell et al [29] propose the gated-Vdd design, in which a transistor is inserted between the ground and each LLC cache line to reduce the leakage current to a [32], [33]. Other efforts have been made to reduce the number of cache accesses, by using snoop filters [34], [35], way predictors [36] or filter caches [37]. Various proposals turn off L1 or L2 cache ways based on different prediction techniques.…”

Section: Power Implicationsmentioning

confidence: 99%

“…JETTY [34] and Blue Gene/P [35] are two proposals to filter the broadcast requests that would miss at destination nodes in order to reduce energy consumption due to cache look-ups. Filtering has also been proposed at source nodes [52], [53] to save energy and bandwidth.…”

Section: Noc and Cache Coherencementioning

confidence: 99%

Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

Lodde¹

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Vorrei prima di tutto ringraziare le persone che mi sono state vicine in questi quattro anni nonostante le centinaia di km che ci separavano: la mia famiglia in Sardegna, Stefania e tutti i miei amici sparsi tra la Sardegna e la Toscana (e qualcuno ultimamente anche un po' più lontano ;) ). Questa tesiè il risultato anche del vostro continuo supporto e affetto.Volviendo a este lado del Mediterráneo, quisiera agradecer en primer lugar a Pepe por haberme dado la oportunidad de hacer el doctorado en el GAP, por su constante seguimiento y soporte a mi trabajo y por su total disponibilidad para ayudarme con cualquier problema.También quiero agradecer a todos los compañeros que han trabajado en los dos laboratorios del GAP en estos años, con que he compartido muchas horas de trabajo, comidas y viajes.Y porúltimo, pero no menos importante, quiero agradecer al resto del personal del DISCA por el gran ambiente de trabajo en que me he encontrado desde el primer día.v AbstractThe cache hierarchy and the Network-on-Chip (NoC) are two key components of chip multiprocessors (CMPs). Most of NoC traffic is due to messages exchanged by the caches according to the coherence protocol. The amount of traffic, the percentage of short and long messages and the traffic pattern in general depend on the cache geometry and the coherence protocol. NoC architecture and the cache hierarchy are indeed tightly coupled, and these two components should be designed and evaluated together to study how varying one's design affects the other one's performance. Furthermore, each component should adjust to match the requirements and exploit the performance of the other one, and vice versa. Usually, messages belonging to different classes are sent through different virtual networks or through NoCs with different bandwidth, thus separating short and long messages. However, other classification of the messages can be done, depending on the type of information they provide: some messages, like data requests, need fields to store information (block address, type of request, etc.); other messages, like acknowledgement messages (ACKs), do not need to specify any information except for the destination node. This second class of messages do no require high NoC bandwidth: latency is far more important, since the destination node is typically blocked waiting for their reception. In this thesis we propose a dedicated network which is able to transmit this second class of messages; the dedicated network is lightweight and fast, and is able to deliver ACKs in a few clock cycles. By reducing ACKs latency and the NoC traffic, it is possible to:• speed-up the invalidation phase during write requests in a system which employs a directory-based coherence protocol• improve the performance of a broadcast-based coherence protocol, reaching performance which is comparable to that of a directory-based protocol but without the additional area overhead due to the directory• implement an efficient and dynamic mapping of cache blocks to the last-level cache banks, aiming to map ...

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Design and implementation of the blue gene/P snoop filter

Cited by 29 publications

References 18 publications

Counting stream registers: An efficient and effective snoop filter architecture

Counting stream registers: An efficient and effective snoop filter architecture

SigNet: Network-on-chip filtering for coarse vector directories

Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

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