Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA

Li, Rongchun; Dou, Yong; Lei, Yuanwu; Ni, Shice; Guo, Song

doi:10.1587/transcom.e95.b.1602

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A Parallel Mode Of Tvda1

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2013

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“…There are two execution modes of TVDA, pipelined one and parallel one, which are described in Fig.2. The pipelined mode of TVDA was proposed in [12] previously, which is shown in Fig.2(a). The arrow implies the execution direction of the algorithm.…”

Section: A Parallel Mode Of Tvdamentioning

confidence: 99%

A fully parallel truncated Viterbi decoder for Software Defined Radio on GPUs

Dou

Liu

et al. 2013

2013 IEEE Wireless Communications and Networking Conference (WCNC)

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In this paper, we propose a fully parallel truncated Viterbi decoder for Software-Defined Radio (SDR) on the Graphics Processing Unit (GPU) platform. We exploit a map-reduce strategy based on the three-point Viterbi decoding algorithm (TVDA) due to the high parallelization potential. The trellis of Viterbi decoding algorithm can be divided into sub-trellises in truncation, which can perform independent forward metrics computing and trace-back procedure in parallel. The parallel Viterbi decoding algorithm is mapped on a GPU named NVIDIA GTX580. The experiment shows that our method shows low BER and 36.0x speedup over a C implementation on a CPU with the frequency of 2.0GHz. At the meantime, our method achieves a performance improvement of 1.2x-3.6x times that of the existing GPU-based implementation.

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Section: A Parallel Mode Of Tvdamentioning

confidence: 99%