Design and Integration for Background Subtraction and Foreground Tracking Algorithm

Abstract

Automatic understanding of events happening at a site is the ultimate goal for many visual surveillance systems. Understanding of events requires that certain lower level computer vision tasks be performed. These include foreground detection, labeling foreground parts, and tracking targets. To achieve these tasks, it is necessary to build background subtraction and foreground tracking in the scene. This paper proposed a hardware-oriental algorithm for background subtraction and foreground tracking. To achieve realtime processing and flexibility, the system is then mapped to a SoC architecture with a single camera. The architecture contains two acceleration units and a programmable micro-processor unit. The usage of micro-processor can provide high flexibility for events understanding in different surveillance by user program. And the proposed accelerator hardware unit is used to increase the entire throughput. Simulation results show that the foreground detection and tracking results are satisfied. Performance of the proposed architecture estimated in terms of the number of clocks is brought forward to justify the real-time processing ability for 30 CIF frames per second.

A low-power 65-nm ASIC implementation of background subtraction

“…to remotely monitor behaviors and activities in large or crowded environments such as shopping malls, traffic and transportation, banks, parks, and hospitals. With the increased availability of fast and cheap computer hardware combined with high quality and low cost image/video sensors, widespread intelligent video analytics systems are becoming popular [1]. However, such applications require high detection accuracy, power-efficient and real-time processing to enable quick decision-making and situation awareness.…”

“…In [1] a hardware-oriented algorithm for background subtraction and foreground tracking is proposed targeting an SoC architecture and utilizing a single camera. The design contains two acceleration units and a programmable micro-processor unit.…”