Design and layout strategies for integrated frequency synthesizers with high spectral purity

Abstract

Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.

Integer boundary spur considerations for fractional‐N PLL based FMCW radar

“…Integer boundary spurs (IBSs) are a particularly infamous performance limitation of fractional-N PLLs [2][3][4]. It is therefore concerning to note that while numerous FMCW radars employ these devices, the impact of IBS on the dechirped beat signal and the resultant range profile has not been reported on.…”