2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)
DOI: 10.1109/isscc.2001.912656
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Design and migration challenges for an Alpha microprocessor in a 0.18 μm copper process

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“…Thus (3) Function is also monotonically decreasing; thus, from (2) and (3) and from the proportionality of with for all clock domains , i.e., we get which shows that the synchronous pipeline performs better energy-wise than the GALS version for the same slowdown factor (or performance penalty) under the assumptions of Lemma 1. This result is in fact a generalization of the optimal voltage-scheduling problem for applications with hard real-time constraints.…”
Section: Choice Of Dynamic Control Strategymentioning
confidence: 67%
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“…Thus (3) Function is also monotonically decreasing; thus, from (2) and (3) and from the proportionality of with for all clock domains , i.e., we get which shows that the synchronous pipeline performs better energy-wise than the GALS version for the same slowdown factor (or performance penalty) under the assumptions of Lemma 1. This result is in fact a generalization of the optimal voltage-scheduling problem for applications with hard real-time constraints.…”
Section: Choice Of Dynamic Control Strategymentioning
confidence: 67%
“…In [2], the designers of the Alpha 21264 microprocessor present the problems encountered when migrating the design to a 180-nm copper process and how the nonscalability of wire delays is affecting this migration process.…”
Section: Motivationmentioning
confidence: 99%
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