Design and modeling challenges for 90 NM and 50 NM

Gerousis, Vassilios

doi:10.1109/cicc.2003.1249417

Cited by 12 publications

(11 citation statements)

References 2 publications

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“…For example, the analog design literature refers to the crossover voltage as the zero temperature coefficient (ZTC) voltage. Surprisingly, it was relatively unknown outside of that literature: it was first mentioned in Park et al [1995], and there have been a few publications since then such as Bellaouar et al [1998], Daga et al [1998], Gerousis [2003], Long et al [2004], and Kanda et al [2001] (under the names "positive/negative temperature dependence" and "temperature inversion"). Almost all of these articles (and those in the analog design literature) seem to have focused mostly on how to take advantage of the (existence of) crossover voltages, for example, to build voltage and current references that are stable over a wider range of temperature.…”

Section: Contributions and Related Workmentioning

confidence: 99%

“…The only articles that address the STA aspects of ITD to some limited extent Daga et al [1998] and Gerousis [2003]. The first article showed that derating delays independently using voltage and temperature results in error.…”

Section: Contributions and Related Workmentioning

confidence: 99%

“…As mentioned in Section 1, the corner doubling approach has already been employed in practice by the some users of STA tools as a temporary solution until these tools can support ITD [Gerousis 2003]. …”

Section: Corner Doublingmentioning

confidence: 99%

“…We want to emphasize that ITD is a real problem (e.g., see Gerousis [2003] about its importance) and the users of the current industrial STA tools insist on its solution. Since none of these tools solve this problem yet, the users usually resort to a temporary solution in which each existing PV corner is combined with two or more temperatures to create new PVT corners.…”

Section: Contributions and Related Workmentioning

confidence: 99%

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Handling inverted temperature dependence in static timing analysis

Dasdan

Hom

2006

ACM Trans. Des. Autom. Electron. Syst.

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In digital circuit design, it is typically assumed that cell delay increases with decreasing voltage and increasing temperature. This assumption is the basis of the cornering approach with cell libraries in static timing analysis (STA). However, this assumption breaks down at low supply voltages because cell delay can decrease with increasing temperature. This phenomenon is caused by a competition between mobility and threshold voltage to dominate cell delay. We refer to this phenomenon as the inverted temperature dependence (ITD). Due to ITD, it becomes very difficult to analytically determine the temperatures that maximize or minimize the delay of a cell or a path. As such, ITD has profound consequences for STA: (1) ITD essentially invalidates the approach of defining corners by independently varying voltage and temperature; (2) ITD makes it more difficult to find short paths, leading to difficulties in detecting hold time violations; and (3) the effect of ITD will worsen as supply voltages decrease and threshold voltage variations increase. This article analyzes the consequences of ITD in STA and proposes a proper handling of ITD in an industrial sign-off STA tool. To the best of our knowledge, this article is the first such work.

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Section: Contributions and Related Workmentioning

confidence: 99%

Section: Contributions and Related Workmentioning

confidence: 99%

Section: Corner Doublingmentioning

confidence: 99%

Section: Contributions and Related Workmentioning

confidence: 99%

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Handling inverted temperature dependence in static timing analysis

Dasdan

Hom

2006

ACM Trans. Des. Autom. Electron. Syst.

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“…This scenario is known as positive temperature dependence or inverted temperature dependence [22]- [24]. Under such circumstances, at higher temperatures, reverse body bias may be applied, without loss in performance, thereby ensuring that the leakage is within the budget.…”

Section: Temperature-leakage Feedback In Circuitsmentioning

confidence: 99%

Body Bias Voltage Computations for Process and Temperature Compensation

Kumar

Kim

Sapatnekar

2008

IEEE Trans. VLSI Syst.

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Abstract-With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. These variations can cause the delay and the leakage of the chip to vary significantly from their expected values, thereby affecting the yield. Circuit designers have proposed the use of threshold voltage modulation techniques to pull back the chip to the nominal operational region. One such scheme, known as Adaptive Body Bias (ABB), has become extremely effective in ensuring optimal performance or leakage savings. Our work provides a means to efficiently compute the body bias voltages required for ensuring high performance operation in gigascale systems. We provide a CAD perspective for determining the exact amount of bias voltages that can compensate both temperature and process variations. Mathematical models for delay and leakage based on minimal tester measurements are built, and a nonlinear optimization problem is formulated to ensure highest frequency operation under all conditions, and thereby minimize the overall circuit leakage. Three different algorithms are presented and their accuracies and run-times are compared. The algorithms have been applied to a wide range of process and temperature corners, for a 65nm and a 45nm technology node based process. A suitable implementation mechanism has also been outlined.

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