Design and Modeling of a Terahertz Transceiver for Intra- and Inter-Chip Communications in Wireless Network-on-Chip Architectures

Abstract

This paper addresses the increasing demand for computing power and the challenges associated with adding more core units to a computer processor. It explores the utilization of System-on-Chip (SoC) technology, which integrates Terahertz (THz) wave communication capabilities for intra- and inter-chip communication, using the concept of Wireless Network-on-Chips (WNoCs). Various types of network topologies are discussed, along with the disadvantages of wired networks. We explore the idea of applying wireless connections among cores and across the chip. Additionally, we describe the WNoC architecture, the flip-chip package, and the THz antenna. Electromagnetic fields are analyzed using a full-wave simulation software, Ansys High Frequency Structure Simulator (HFSS). The simulation is conducted with dipole and zigzag antennas communicating within the chip at resonant frequencies of 446 GHz and 462.5 GHz, with transmission coefficients of around −28 dB and −33 to −41 dB, respectively. Transmission coefficient characterization, path loss analysis, a study of electric field distribution, and a basic link budget for transmission are provided. Furthermore, the feasibility of calculated transmission power is validated in cases of high insertion loss, ensuring that the achieved energy expenditure is less than 1 pJ/bit. Finally, employing a similar setup, we study intra-chip communication using the same antennas. Simulation results indicate that the zigzag antenna exhibits a higher electric field magnitude compared with the dipole antenna across the simulated chip structure. We conclude that transmission occurs through reflection from the ground plane of a printed circuit board (PCB), as evidenced by the electric field distribution.