Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Abstract

This article presents the design and optimisation of a sub‐1 GHz class‐F ultra‐low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class‐F PA. The ET consist of a pre‐amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class‐F with gate‐to‐drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long‐range low power wireless local area network IEEE 802.11ah standard. The inductor‐less design for ET supply bias reduces the chip layout size to 0.13 mm2 only.

Comparative Analysis of Design Parameters for Modern Radio Frequency Complementary Metal Oxide Semiconductor Ultra-Low Power Amplifier Architecture Trends

“…The analysis was performed with reference to the input power (in dBm). Concerning BLE RF PAs, Integrated Analogue Pre-Distorters (APDs) [4] and class-F designs with reconfigurable off-chip inter-stage matching networks [10] have a low PAE compared to class-E [3] and class-D [6] design architectures.…”

“…Due to class-2 BLE ISM band designs, the remaining devices offer acceptable output powers between 1 and 4 dBm. Due to the sub-1 GHz band, the IEEE 802.11 ah WiFi HaLow offers a long range of up to 1 km, as observed in [7][8][9][10] PA design architectures.…”

“…The DPA with fixed inter-stage capacitances [6] and class-F designs with feedback using ET supply bias [10] are ultra-low power (ULP) designs compared to the rest of the proposed architectures. The MOS architectures in both designs are biased in the subthreshold region.…”

PVT Analysis and Behavioral Modeling of Doherty and Envelope Tracking RF ULP Power Amplifiers using 65 nm CMOS Technology

“…Layout of Silicon Footprint Showing 45% Reduction for ET PA reported in[7] and[9]; (a) Layout of ULP DPA (0.29 mm 2 Silicon Layout Footprint), (b) Layout of ULP ET PA (0.13 mm 2 Silicon Layout Footprint)…”