Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE

Abstract

Abstract. This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for the standards GSM/GPRS/EDGE, in order to reduce power consumption and die area as desired for cellular applications. To this end, the hardware implementation of a channel shortening pre-filter combined with a delayed decision-feedback sequence estimator (DFSE) for channel equalization is described. The digital receiver back-end including a flexible Viterbi decoder implementation is presented and hardware savings that can be achieved by using hard-decisions are discussed. Design trade-offs are highlighted to prove the efficiency of the implemented 2.5G multimode architecture. The ASIC in 0.13 μm CMOS technology occupies 1.0 mm 2 and dissipates only 1.3 mW in fastest EDGE data transmission mode.

Efficient vlsi implementation of reduced-state sequence estimation for wireless communications

“…The stored partial reference signals are simply combined by addition to generate the final e(st−1,st) according to (6). It has been shown in [9] for the case of a DDFSE that the number of multiplications can be drastically reduced by precomputation of es. In the following we discuss the trade-off between computational and storage complexity for the more general case of RSSE and include also the possibility of pre-computing e b .…”

“…A VLSI implementation of a delayed-decision feedback sequence estimator (DDFSE), a special case of RSSE, for 2.5G EDGE and for 2.75G Evolved EDGE (E-EDGE) [7] has been published in [8] and [9], respectively. However, in literature there is a lack of RSSE design space exploration for systems with moderate throughput requirements using higher order modulation.…”

“…We apply the pre-computation approach presented in [9] for DDFSE to the more general RSSE. The presented design space exploration allows for efficient VLSI architectures tailored to given design constraints.…”