Design and Optimization of an ARM Cortex-M Based SoC for TCP/IP Communication in High Temperature Applications

Stuckenberg, Tobias; Gottschlich, M.; Nolting, Stephan; Blume, Holger

doi:10.1007/978-3-030-27562-4_12

Cited by 2 publications

(1 citation statement)

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“…In case of a harsh environment system, sensor and control data are the most common types of information that are transferred. The required data rates of such information usually reach few kbit/s, but modern powerline communication standards can provide several Mbit/s, which enables the connection of over 100 sensors and actors onto a single wire [27]. The main challenge for communication systems in a harsh environment is to provide a stable and reliable link even at low Signal-to-Noise-Ratio (SNR) or over frequency fading channels.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Gesper

Weißbrich

Stuckenberg

et al. 2020

Int J Parallel Prog

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Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 $$\upmu $$ μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5$$\times $$ × higher performance and 2.4$$\times $$ × higher computational energy efficiency at a 1.6$$\times $$ × larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

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Section: Introductionmentioning

confidence: 99%