Design and optimization of DTSCR for high-speed I/O ESD protection of on-chip ICs

Abstract

A gate-assisted and diode-triggered silicon controlled rectifier with the waffle layout (GDTSCR-WL) is proposed and investigated. By designing the waffle layout in the conventional diode-triggered silicon controlled rectifier (DTSCR), the electrostatic discharge (ESD) performance of the GDTSCR-WL can be used to optimize remarkably, especially for the parasitic capacitance, clamping voltage (V C), and current handling ability. By further introducing the gate-assisted trigger effect, the GDTSCR-WL can discharge the ESD-induced current more quickly. The technology computer aided design (TCAD) simulations and electrical test results indicate that the GDTSCR-WL has extraordinary ESD performance, such as a V C of 1.24 V, a turn-on resistance of 0.14 Ω, and the large figure of merit of 5.76 mA μm−2, outperforming dual-diode string and DTSCR. Moreover, by adjusting the width W 1 and space W 2 of diode blocks with the waffle layout, the capacitance of the GDTSCR-WL can be continuously decreased from 140 to 92 fF. The optimized GDTSCR-WL with a small capacitance can pass the 8 kV human body model test, providing an efficient and optional solution for high-speed input/output ESD protection of on-chip ICs.