Design and optimization of multithreshold cmos (mtcmos) circuits

Anis, Mohab; Areibi, Shawki; Elmasry, M.I.

doi:10.1109/tcad.2003.818127

Cited by 157 publications

(82 citation statements)

References 16 publications

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“…Using the Finite Element Modeling characterization of SG-FET in [16], we sized the power switches in both 2D cases according to [18], in order to achieve a target IR-drop under 20 mV on them for the Accurate dynamic power and rail analysis with the switchable power domain functioning and turned off were performed using Cadence VoltageStorm to evaluate the power gating efficiency. The switching activity was set to 0.2.…”

Section: Experimental Setup and Resultsmentioning

confidence: 99%

Advanced NEMS-based power management for 3D Stacked Integrated Circuits

Enachescu

Voicu

Cotofana

2010

2010 International Conference on Energy Aware Computing

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Abstract-In this paper we introduce a novel power management architecture for 3D Through Silicon Vias based integration technology. Our approach relies on the synergy of two new technological developments as follows: (i) we utilize a NanoElectroMechanical (NEM) device, the Suspended Gate FET (SG-FET), as sleep transistor; and (ii) we make use of the 3D potential by placing the sleep transistor (the entire power management infrastructure) on a dedicated tier of the 3D stacked Integrated Circuit. Due to the extreme low leakage current of the SG-FET our proposal results in 2 orders of magnitude static power reduction, when compared with equivalent counterparts based on traditional CMOS devices. The SG-FET power switch requires about 4x more area when compared to bulk CMOS, however, due to the 3D integration which allows for heterogeneous dies to be stacked, the power gating devices can be placed to a low cost dedicated layer, which also results in a substantial IR-drop reduction with minimum impact on leakage.

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Section: Experimental Setup and Resultsmentioning

confidence: 99%

Advanced NEMS-based power management for 3D Stacked Integrated Circuits

Enachescu

Voicu

Cotofana

2010

2010 International Conference on Energy Aware Computing

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“…To reduce the overall power consumption, the well known technique is to scale supply voltage, but this scaling results into exponential increase in the leakage current [6]. The sub threshold leakage current (I leakage) can be assessed as (approximately) [7] .Ileakage = Ioe(Vgs − Vth)/ηVт C ox is the gate oxide capacitance; (W/L) is the ratio of width to length of the leakage MOS device. µ 0 is the zero bias mobility.…”

Section: 1mentioning

confidence: 99%

Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology

Pandey¹,

Akashe²

2014

IJCA

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Reduction of power dissipation is one of the most important challenges in VLSI circuit design. Due to scaling, sub threshold leakage current plays a dominant role in total power dissipation. This paper illustrates application of power saving SVL technique on 2:1 NAND MUX architecture. This application offers significant reduction in leakage power and leakage current viz-a-viz previous techniques. Self controllable Voltage Level Circuit (SVL) technique drastically reduces stand by leakage power and leakage current of CMOS logic circuits. This technique compare the optimization of leakage current and leakage power using two different design of 2:1 MUX. First is conventional MUX and other one is NAND based 2:1 MUX. The performance of this designed circuit is realized on a standard 45nm technology by using 0.7v supply voltage. It is easily concluded that this 2:1 nand based MUX achieves 651.9 Pw leakage power (Pst) and leakage current 1.020nA in standby mode, Where as conventional MUX achieved 2.04nA leakage current and 0.5nW leakage power.

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“…This technique has its own advantages and disadvantages. [7], [8] The basic circuit diagram of MTCMOS circuit is shown in Fig.(f). The circuit diagram of MTCMOS circuit implemented on cadence virtuoso design editor is shown in Fig.(g).…”

Section: Mtcmosmentioning

confidence: 99%