Design and Optimization of Timing Errors on Swapping of Threshold Voltage

B, Saurab.; Chavan, Arunkumar P

doi:10.1109/mysurucon52639.2021.9641564

Cited by 1 publication

(3 citation statements)

References 11 publications

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“…With the selected features, the structure of ANN is illustrated in Figure 8. The input layer accepts the features including setup time (t su ), hold time (t hd ), data transition (s d ), clock transition (s ck ), and output load capacitance (c ld ), while the output layer produces the clock-to-q delay (d cq ) as the function of input features shown in (3).…”

Section: Dcq = F(tsu Thd Sd Sck Cld)mentioning

confidence: 99%

“…transition (sck), and output load capacitance (cld), while the output layer produces the clockto-q delay (dcq) as the function of input features shown in (3).…”

Section: Dcq = F(tsu Thd Sd Sck Cld)mentioning

confidence: 99%

“…With the development of the microelectronics craft technique, modern IC design attaches great importance to the Performance, Power, and Area (PPA) of chips [1][2][3]. The technique of reducing the supply voltage to near-threshold voltage (NTV) region is receiving more attention in recent years due to remarkable energy efficiency improvement but suffers from severe challenges of performance variation for Static Timing Analysis (STA) [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

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Timing Analysis and Optimization Method with Interdependent Flip-Flop Timing Model for Near-Threshold Design

2022

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Near-threshold Voltage (NTV) design is receiving wide attention due to remarkable energy efficiency improvement at the cost of performance degradation. The interdependency between the setup–hold time and clock-to-q delay of flip-flops has been exploited in the Super-threshold Voltage (STV) domain to improve circuit performance but faces the severe challenge of nonlinear relationship and wider effective coverage in the NTV region, which prevents the application of interdependent flip-flop model for timing analysis and optimization for NTV design. In this paper, a novel interdependent flip-flop timing model is proposed by Artificial Neural Network (ANN) to predict the clock-to-q delay with training data generated by SPICE simulation in a restricted hexagonal area of the two-dimensional setup-hold time space. By integrating the proposed model into Static Timing Analysis (STA) flow, a novel iterative optimization method is proposed to improve performance for NVT circuits based on a Genetic Algorithm (GA). The proposed timing analysis and optimization method were validated under Semiconductor Manufacturing International Corporation (SMIC) 40 nm process at the voltage of 0.6 V with the International Symposium on Circuits and Systems (ISCAS)’89 benchmark circuits. Experimental results demonstrate that the ANN-based interdependent timing model for flip-flop achieves considerable accurate prediction with the Mean Absolute Relative Error (MARE) of less than 0.69%. The minimum clock periods for ISCAS’89 benchmark circuits are reduced by 1.70~6.28% compared to traditional STA results without any setup and hold violations and hardware cost, which achieves at most 6.7% performance improvement for NTV design.

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Section: Dcq = F(tsu Thd Sd Sck Cld)mentioning

confidence: 99%

“…transition (sck), and output load capacitance (cld), while the output layer produces the clockto-q delay (dcq) as the function of input features shown in (3).…”

Section: Dcq = F(tsu Thd Sd Sck Cld)mentioning

confidence: 99%