Design and performance analysis of an ultra‐high‐speed 5‐2 compressor

Abstract

A novel ultra‐high‐speed 5‐2 compressor is presented and discussed in this paper. The proposed structure is developed by modifying the truth table focusing on the carry rippling problem. By reducing the number of the states in the truth table and the complexity of the structure, the total delay is reduced while the power and active area are also improved. The proposed compressor is compared with the best recently reported ones where the designed architecture shows 9%–80% improvement in power delay product (PDP). For a better demonstration of the advantages, the proposed structure is placed in the body of a 16 × 16‐bit multiplier and is compared with the other multipliers consisting of the other 5‐2 compressor architectures. The results indicate an improvement equal to 13%. It must also be mentioned that the gate‐level delay calculation is emphasized in this paper, where a precise estimation method is utilized considering the capacitances at the middle‐stage nodes. Based on the calculations, the designed circuit has the minimum gate‐level delay compared to the other related works due to its minimal intermediate connections. For simulating the proposed structure, a standard CMOS 0.18‐μm process along with HSPICE software is used, where the results show a delay of 266.5 ps with a power consumption of 164 μw.

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

“…During recent years, various gate‐level and transistor‐level architectures have been offered for 4:2 and 5:2 compressors [17–19] with different techniques such as the gate‐diffusion input (GDI) by considering area reduction and output swing cost [20]. Also, the complementary metal‐oxide‐semiconductor (CMOS) was considered to improve the speed of these compressors (even for the 7:2 compressor) by resolving the carry rippling problem [21, 22]. The second one is characterised by the driving capability and robustness against process variation with large area occupation cost.…”