Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit

Khan, Esam; El-Kharashi, M. Watheq; Gebali, Fayez; Abd-El-Barr, Mostafa

doi:10.1109/tcsi.2007.910539

Cited by 24 publications

(23 citation statements)

References 19 publications

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“…Throughput is calculated using formulae, Throughput of the unified architecture is also comparatively high. The throughput of unified architecture achieves around 845 mbps for MD5 algorithm and 676mbps for proposed The proposed design is compared with existing hardware implementation [9] and it found that the proposed architectures is better in all means that is, area utilization , frequency and throughput all very good than the results presented in [9]. And also power analysis is made for proposed architecture and shows it consumes only 7.09 mW which is not made in the previous work.…”

Section: Resultsmentioning

confidence: 81%

A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio

Thulasimani¹,

Madheswaran²

2010

IJCEE

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Abstract-Software Radio terminals being able to reconfigure to various radio access systems, will require robust security mechanism to protect the mobile terminals from unauthorized access and to ensure the integrity of internal process involved in reconfiguration when exchanging information with the network. This paper aims to propose an energy efficient reconfigurable hardware architecture which supports data integrity for the secured downloading of software in reconfigurable receivers.

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Section: Resultsmentioning

confidence: 81%

A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio

Thulasimani¹,

Madheswaran²

2010

IJCEE

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“…The HMAC-hash unit, proposed by Khan et al (2007), gets a message, hashes it using one of six hash functions: MD5, SHA-1, RIPEMD-160, HMAC-MD5, HMAC-SHA-1, and HMAC-RIPEMD-160, and produces the resulting hash value. Figure 1 shows a block diagram of this HMAC-hash unit.…”

Section: The Hmac-hash Unitmentioning

confidence: 99%

“…It passes each block to the hash unit. The hash unit hashes the message (or the key, if required) using the unified hash algorithm discussed by Khan et al (2007). Signals Mode and Alg are used to reconfigure the HMAC unit and select one hash function, as shown in Table 1.…”

Section: The Hmac-hash Unitmentioning

confidence: 99%

“…In a previous work (Khan et al, 2007), we designed a reconfigurable unit that implements the HMAC algorithm. This hash unit was designed based on a unified algorithm that implements three hash functions, MD5, SHA-1, and RIPEMD-160.…”

Section: Introductionmentioning

confidence: 99%

“…The HMAC unit described by Khan et al (2007) implements a general version of the HMAC algorithm, where a key of any length is allowed. In this paper, we implement another version of the HMAC unit that uses fixed key size.…”

Section: Introductionmentioning

confidence: 99%

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Design Space Exploration of a Reconfigurable HMAC-Hash Unit

Khan

El-Kharashi

Gebali

et al. 2006

2006 ITI 4th International Conference on Information &Amp; Communications Technology

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A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm

Sun,

Liu,

Cheng

et al. 2023

Circuit Theory & Apps

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In this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is designed based on SMIC 14 nm process. Since the key issue of limiting the throughput of RC4 encryption algorithm is the swapping operation of S‐box, this proposed design is capable of achieving four swapping operations of S‐box within a clock cycle by utilizing fully combinational logic designs and advanced computations. All 256 swapping operations of key scheduling algorithm (KSA) can be done in 64 clock cycles. Moreover, the novel design greatly improves the encryption efficiency of RC4 since each clock cycle offers 4 bytes of key stream. The whole area can be further optimized by reusing the existing modules, and a lightweight countermeasure is embedded into the RC4 design to break the correlation between the processed data and power dissipation against differential power analysis (DPA) attacks. Finally, the whole design is assessed by the SMIC 14 nm process design kits (PDK). The corresponding clock frequency, throughput, area, and latency, respectively, are achieved as 1 GHz, 32 Gbps, 51,596 m2, and 74 clock cycles.

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Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit

Cited by 24 publications

References 19 publications

A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio

A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio

Design Space Exploration of a Reconfigurable HMAC-Hash Unit

A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm

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