“…This idea was further refined in [40] where the SRO signal was sub-sampled with a D-type flip-flop at a frequency lower (or even substantially lower) than ω 0 to get a shift-register filled with a set of 1-bit samples that represents the SRO output phase. The complexity of the required digital hardware is orders of magnitude simpler than with conventional IQ receivers and allows building of complete BPSK, QPSK, or 8PSK receivers [41] with very few resources, without spoiling the main point of SR reception: simplicity. The same net effect can be achieved by sampling several RCdelayed versions of the SRO output [42]- [44].…”